[Keyboard] Oddball keyboard and optical sensor update (#10450)
* Add oddballl v2 - add CPI options - add scroll support - add click-and-drag support - PMW3360 implementation - ADNS9800 improvements * Set default make directory * Update readme with PMW config * Change bootloader * Update unused pins on v2 * Remove diode switch * Move bootloader selection to keyboard version level * Change default keyboard folder to v1 * Move sensor selection to keymap * Remove PK debounce * Change to only send mouse report on change * Change CPI function cpi type * Remove EEPROM state check * Update CPI to only change on key down * Fix incorrect F8 in keymap * Add v2.1 with more convenient controller pinout * Add keyboard readmes * Update keyboards/oddball/pmw/pmw3360_srom_0x04.h Remove direct AVR reference Co-authored-by: Ryan <fauxpark@gmail.com> * Remove direct AVR reference Co-authored-by: Ryan <fauxpark@gmail.com> Co-authored-by: Alexander Tulloh <alex@riberry.io> Co-authored-by: Ryan <fauxpark@gmail.com>
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								keyboards/oddball/adns/adns.c
									
										
									
									
									
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								keyboards/oddball/adns/adns.c
									
										
									
									
									
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/* Copyright 2020 Alexander Tulloh
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 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#include "spi_master.h"
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#include "quantum.h"
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#include "adns9800_srom_A6.h"
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#include "adns.h"
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// registers
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#define REG_Product_ID                           0x00
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#define REG_Revision_ID                          0x01
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#define REG_Motion                               0x02
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#define REG_Delta_X_L                            0x03
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#define REG_Delta_X_H                            0x04
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#define REG_Delta_Y_L                            0x05
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#define REG_Delta_Y_H                            0x06
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#define REG_SQUAL                                0x07
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#define REG_Pixel_Sum                            0x08
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#define REG_Maximum_Pixel                        0x09
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#define REG_Minimum_Pixel                        0x0a
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#define REG_Shutter_Lower                        0x0b
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#define REG_Shutter_Upper                        0x0c
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#define REG_Frame_Period_Lower                   0x0d
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#define REG_Frame_Period_Upper                   0x0e
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#define REG_Configuration_I                      0x0f
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#define REG_Configuration_II                     0x10
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#define REG_Frame_Capture                        0x12
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#define REG_SROM_Enable                          0x13
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#define REG_Run_Downshift                        0x14
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#define REG_Rest1_Rate                           0x15
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#define REG_Rest1_Downshift                      0x16
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#define REG_Rest2_Rate                           0x17
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#define REG_Rest2_Downshift                      0x18
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#define REG_Rest3_Rate                           0x19
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#define REG_Frame_Period_Max_Bound_Lower         0x1a
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#define REG_Frame_Period_Max_Bound_Upper         0x1b
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#define REG_Frame_Period_Min_Bound_Lower         0x1c
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#define REG_Frame_Period_Min_Bound_Upper         0x1d
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#define REG_Shutter_Max_Bound_Lower              0x1e
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#define REG_Shutter_Max_Bound_Upper              0x1f
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#define REG_LASER_CTRL0                          0x20
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#define REG_Observation                          0x24
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#define REG_Data_Out_Lower                       0x25
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#define REG_Data_Out_Upper                       0x26
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#define REG_SROM_ID                              0x2a
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#define REG_Lift_Detection_Thr                   0x2e
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#define REG_Configuration_V                      0x2f
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#define REG_Configuration_IV                     0x39
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#define REG_Power_Up_Reset                       0x3a
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#define REG_Shutdown                             0x3b
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#define REG_Inverse_Product_ID                   0x3f
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#define REG_Motion_Burst                         0x50
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#define REG_SROM_Load_Burst                      0x62
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#define REG_Pixel_Burst                          0x64
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#define ADNS_CLOCK_SPEED 2000000
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#define MIN_CPI 200
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#define MAX_CPI 8200
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#define CPI_STEP 200
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#define CLAMP_CPI(value) value < MIN_CPI ? MIN_CPI : value > MAX_CPI ? MAX_CPI : value
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#define SPI_MODE 3
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#define SPI_DIVISOR (F_CPU / ADNS_CLOCK_SPEED)
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#define US_BETWEEN_WRITES 120
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#define US_BETWEEN_READS 20
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#define US_BEFORE_MOTION 100
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#define MSB1 0x80
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extern const uint16_t adns_firmware_length;
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extern const uint8_t adns_firmware_data[];
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void adns_spi_start(void){
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    spi_start(SPI_SS_PIN, false, SPI_MODE, SPI_DIVISOR);
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}
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void adns_write(uint8_t reg_addr, uint8_t data){
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    adns_spi_start();
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    spi_write(reg_addr | MSB1);
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    spi_write(data);
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    spi_stop();
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    wait_us(US_BETWEEN_WRITES);
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}
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uint8_t adns_read(uint8_t reg_addr){
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    adns_spi_start();
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    spi_write(reg_addr & 0x7f );
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    uint8_t data = spi_read();
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    spi_stop();
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    wait_us(US_BETWEEN_READS);
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    return data;
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}
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void adns_init() {
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    setPinOutput(SPI_SS_PIN);
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    spi_init();
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    // reboot
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    adns_write(REG_Power_Up_Reset, 0x5a);
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    wait_ms(50);
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    // read registers and discard
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    adns_read(REG_Motion);
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    adns_read(REG_Delta_X_L);
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    adns_read(REG_Delta_X_H);
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    adns_read(REG_Delta_Y_L);
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    adns_read(REG_Delta_Y_H);
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    // upload firmware
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    // 3k firmware mode
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    adns_write(REG_Configuration_IV, 0x02);
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    // enable initialisation
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    adns_write(REG_SROM_Enable, 0x1d);
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    // wait a frame
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    wait_ms(10);
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    // start SROM download
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    adns_write(REG_SROM_Enable, 0x18);
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    // write the SROM file
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    adns_spi_start();
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    spi_write(REG_SROM_Load_Burst | 0x80);
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    wait_us(15);
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    // send all bytes of the firmware
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    unsigned char c;
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    for(int i = 0; i < adns_firmware_length; i++){
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        c = (unsigned char)pgm_read_byte(adns_firmware_data + i);
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        spi_write(c);
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        wait_us(15);
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    }
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    spi_stop();
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    wait_ms(10);
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    // enable laser
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    uint8_t laser_ctrl0 = adns_read(REG_LASER_CTRL0);
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    adns_write(REG_LASER_CTRL0, laser_ctrl0 & 0xf0);
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}
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config_adns_t adns_get_config(void) {
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    uint8_t config_1 = adns_read(REG_Configuration_I);
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    return (config_adns_t){ (config_1 & 0xFF) * CPI_STEP };
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}
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void adns_set_config(config_adns_t config) {
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    uint8_t config_1 = (CLAMP_CPI(config.cpi) / CPI_STEP) & 0xFF;
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    adns_write(REG_Configuration_I, config_1);
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}
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static int16_t convertDeltaToInt(uint8_t high, uint8_t low){
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    // join bytes into twos compliment
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    uint16_t twos_comp = (high << 8) | low;
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    // convert twos comp to int
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    if (twos_comp & 0x8000)
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        return -1 * (~twos_comp + 1);
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    return twos_comp;
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}
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report_adns_t adns_get_report(void) {
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    report_adns_t report = {0, 0};
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    adns_spi_start();
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    // start burst mode
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    spi_write(REG_Motion_Burst & 0x7f);
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    wait_us(US_BEFORE_MOTION);
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    uint8_t motion = spi_read();
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    if(motion & 0x80) {
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        // clear observation register
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        spi_read();
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        // delta registers
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        uint8_t delta_x_l = spi_read();
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        uint8_t delta_x_h = spi_read();
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        uint8_t delta_y_l = spi_read();
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        uint8_t delta_y_h = spi_read();
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        report.x = convertDeltaToInt(delta_x_h, delta_x_l);
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        report.y = convertDeltaToInt(delta_y_h, delta_y_l);
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    }
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    // clear residual motion
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    spi_write(REG_Motion & 0x7f);
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    spi_stop();
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    return report;
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}
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