When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale).

2011-10-12 02:27:22 +00:00 · 2011-10-12 02:27:22 +00:00 · c15eaa5dae
commit c15eaa5dae
parent 1a4a26271e
2 changed files with 3 additions and 2 deletions
--- a/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
+++ b/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c
@ -68,7 +68,7 @@ void USB_Init(
 	if (!(USB_Options & USB_OPT_MANUAL_PLL))
 	{
 		#if defined(USB_SERIES_4_AVR)
-		PLLFRQ = ((1 << PLLUSB) | (1 << PDIV3) | (1 << PDIV1));
+		PLLFRQ = (1 << PDIV2);
 		#endif
 	}