GC9xxx LCD family drivers (GC9107 and GC9A01) (#23091)
Co-authored-by: Nick Brassel <nick@tzarc.org> Co-authored-by: jack <0x6A73@pm.me> Co-authored-by: Joel Challis <git@zvecr.com> Co-authored-by: フィルターペーパー <76888457+filterpaper@users.noreply.github.com> Co-authored-by: rookiebwoy <81021475+rookiebwoy@users.noreply.github.com> Fixup boardsource/equals (#23106) Fix make clean test:os_detection (#23112) Fix make clean test:os_detection (#23112)" Fixup boardsource/equals (#23106)"
This commit is contained in:
Fernando Birra
GitHub
parent
75d11e0421
commit
a82b0628b3
11 changed files with 490 additions and 133 deletions
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// Copyright 2021 Paul Cotter (@gr1mr3aver)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Quantum Painter GC9A01 command opcodes
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Level 1 command opcodes
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#define GC9A01_GET_ID_INFO 0x04 // Get ID information
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#define GC9A01_GET_STATUS 0x09 // Get status
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#define GC9A01_CMD_SLEEP_ON 0x10 // Enter sleep mode
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#define GC9A01_CMD_SLEEP_OFF 0x11 // Exit sleep mode
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#define GC9A01_CMD_PARTIAL_ON 0x12 // Enter partial mode
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#define GC9A01_CMD_PARTIAL_OFF 0x13 // Exit partial mode
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#define GC9A01_CMD_INVERT_ON 0x20 // Enter inverted mode
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#define GC9A01_CMD_INVERT_OFF 0x21 // Exit inverted mode
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#define GC9A01_CMD_DISPLAY_OFF 0x28 // Disable display
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#define GC9A01_CMD_DISPLAY_ON 0x29 // Enable display
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#define GC9A01_SET_COL_ADDR 0x2A // Set column address
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#define GC9A01_SET_PAGE_ADDR 0x2B // Set page address
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#define GC9A01_SET_MEM 0x2C // Set memory
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#define GC9A01_SET_PARTIAL_AREA 0x30 // Set partial area
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#define GC9A01_SET_VSCROLL 0x33 // Set vertical scroll def
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#define GC9A01_CMD_TEARING_ON 0x34 // Tearing line enabled
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#define GC9A01_CMD_TEARING_OFF 0x35 // Tearing line disabled
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#define GC9A01_SET_MEM_ACS_CTL 0x36 // Set mem access ctl
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#define GC9A01_SET_VSCROLL_ADDR 0x37 // Set vscroll start addr
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#define GC9A01_CMD_IDLE_OFF 0x38 // Exit idle mode
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#define GC9A01_CMD_IDLE_ON 0x39 // Enter idle mode
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#define GC9A01_SET_PIX_FMT 0x3A // Set pixel format
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#define GC9A01_SET_MEM_CONT 0x3C // Set memory continue
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#define GC9A01_SET_TEAR_SCANLINE 0x44 // Set tearing scanline
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#define GC9A01_GET_TEAR_SCANLINE 0x45 // Get tearing scanline
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#define GC9A01_SET_BRIGHTNESS 0x51 // Set brightness
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#define GC9A01_SET_DISPLAY_CTL 0x53 // Set display ctl
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#define GC9A01_GET_ID1 0xDA // Get ID1
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#define GC9A01_GET_ID2 0xDB // Get ID2
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#define GC9A01_GET_ID3 0xDC // Get ID3
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Level 2 command opcodes
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#define GC9A01_SET_RGB_IF_SIG_CTL 0xB0 // RGB IF signal ctl
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#define GC9A01_SET_BLANKING_PORCH_CTL 0xB5 // Set blanking porch ctl
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#define GC9A01_SET_FUNCTION_CTL 0xB6 // Set function ctl
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#define GC9A01_SET_TEARING_EFFECT 0xBA // Set backlight ctl 3
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#define GC9A01_SET_IF_CTL 0xF6 // Set interface control
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Level 3 command opcodes
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#define GC9A01_SET_FRAME_RATE 0xE8 // Set frame rate
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#define GC9A01_SET_SPI_2DATA 0xE9 // Set frame rate
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#define GC9A01_SET_POWER_CTL_1 0xC1 // Set power ctl 1
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#define GC9A01_SET_POWER_CTL_2 0xC3 // Set power ctl 2
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#define GC9A01_SET_POWER_CTL_3 0xC4 // Set power ctl 3
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#define GC9A01_SET_POWER_CTL_4 0xC9 // Set power ctl 4
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#define GC9A01_SET_POWER_CTL_7 0xA7 // Set power ctl 7
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#define GC9A01_SET_INTER_REG_ENABLE1 0xFE // Enable Inter Register 1
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#define GC9A01_SET_INTER_REG_ENABLE2 0xEF // Enable Inter Register 2
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#define GC9A01_SET_GAMMA1 0xF0 //
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#define GC9A01_SET_GAMMA2 0xF1
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#define GC9A01_SET_GAMMA3 0xF2
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#define GC9A01_SET_GAMMA4 0xF3
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// MADCTL Flags
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#define GC9A01_MADCTL_MY 0b10000000
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#define GC9A01_MADCTL_MX 0b01000000
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#define GC9A01_MADCTL_MV 0b00100000
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#define GC9A01_MADCTL_ML 0b00010000
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#define GC9A01_MADCTL_RGB 0b00000000
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#define GC9A01_MADCTL_BGR 0b00001000
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#define GC9A01_MADCTL_MH 0b00000100
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114
drivers/painter/gc9xxx/qp_gc9107.c
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114
drivers/painter/gc9xxx/qp_gc9107.c
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// Copyright 2024 Fernando Birra
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "qp_internal.h"
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#include "qp_comms.h"
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#include "qp_gc9107.h"
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#include "qp_gc9xxx_opcodes.h"
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#include "qp_gc9107_opcodes.h"
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#include "qp_tft_panel.h"
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Driver storage
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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tft_panel_dc_reset_painter_device_t gc9107_drivers[GC9107_NUM_DEVICES] = {0};
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Initialization
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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__attribute__((weak)) bool qp_gc9107_init(painter_device_t device, painter_rotation_t rotation) {
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// A lot of these "unknown" opcodes are sourced from other OSS projects and are seemingly required for this display to function.
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// clang-format off
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const uint8_t gc9107_init_sequence[] = {
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GC9XXX_SET_INTER_REG_ENABLE1, 5, 0,
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GC9XXX_SET_INTER_REG_ENABLE2, 5, 0,
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GC9107_SET_FUNCTION_CTL6, 0, 1, GC9107_ALLOW_SET_COMPLEMENT_RGB | 0x08 | GC9107_ALLOW_SET_FRAMERATE,
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GC9107_SET_COMPLEMENT_RGB, 0, 1, GC9107_COMPLEMENT_WITH_LSB,
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0xAB, 0, 1, 0x0E,
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GC9107_SET_FRAME_RATE, 0, 1, 0x19,
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GC9XXX_SET_PIXEL_FORMAT, 0, 1, GC9107_PIXEL_FORMAT_16_BPP_IFPF,
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GC9XXX_CMD_SLEEP_OFF, 120, 0,
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GC9XXX_CMD_DISPLAY_ON, 20, 0
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};
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// clang-format on
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qp_comms_bulk_command_sequence(device, gc9107_init_sequence, sizeof(gc9107_init_sequence));
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// Configure the rotation (i.e. the ordering and direction of memory writes in GRAM)
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const uint8_t madctl[] = {
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[QP_ROTATION_0] = GC9XXX_MADCTL_BGR,
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[QP_ROTATION_90] = GC9XXX_MADCTL_BGR | GC9XXX_MADCTL_MX | GC9XXX_MADCTL_MV,
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[QP_ROTATION_180] = GC9XXX_MADCTL_BGR | GC9XXX_MADCTL_MX | GC9XXX_MADCTL_MY,
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[QP_ROTATION_270] = GC9XXX_MADCTL_BGR | GC9XXX_MADCTL_MV | GC9XXX_MADCTL_MY,
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};
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qp_comms_command_databyte(device, GC9XXX_SET_MEM_ACS_CTL, madctl[rotation]);
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return true;
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}
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Driver vtable
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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const tft_panel_dc_reset_painter_driver_vtable_t gc9107_driver_vtable = {
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.base =
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{
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.init = qp_gc9107_init,
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.power = qp_tft_panel_power,
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.clear = qp_tft_panel_clear,
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.flush = qp_tft_panel_flush,
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.pixdata = qp_tft_panel_pixdata,
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.viewport = qp_tft_panel_viewport,
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.palette_convert = qp_tft_panel_palette_convert_rgb565_swapped,
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.append_pixels = qp_tft_panel_append_pixels_rgb565,
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.append_pixdata = qp_tft_panel_append_pixdata,
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},
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.num_window_bytes = 2,
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.swap_window_coords = false,
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.opcodes =
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{
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.display_on = GC9XXX_CMD_DISPLAY_ON,
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.display_off = GC9XXX_CMD_DISPLAY_OFF,
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.set_column_address = GC9XXX_SET_COL_ADDR,
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.set_row_address = GC9XXX_SET_ROW_ADDR,
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.enable_writes = GC9XXX_SET_MEM,
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},
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};
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#ifdef QUANTUM_PAINTER_GC9107_SPI_ENABLE
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// Factory function for creating a handle to the GC9107 device
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painter_device_t qp_gc9107_make_spi_device(uint16_t panel_width, uint16_t panel_height, pin_t chip_select_pin, pin_t dc_pin, pin_t reset_pin, uint16_t spi_divisor, int spi_mode) {
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for (uint32_t i = 0; i < GC9107_NUM_DEVICES; ++i) {
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tft_panel_dc_reset_painter_device_t *driver = &gc9107_drivers[i];
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if (!driver->base.driver_vtable) {
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driver->base.driver_vtable = (const painter_driver_vtable_t *)&gc9107_driver_vtable;
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driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
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driver->base.native_bits_per_pixel = 16; // RGB565
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driver->base.panel_width = panel_width;
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driver->base.panel_height = panel_height;
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driver->base.rotation = QP_ROTATION_0;
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driver->base.offset_x = 2;
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driver->base.offset_y = 1;
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// SPI and other pin configuration
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driver->base.comms_config = &driver->spi_dc_reset_config;
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driver->spi_dc_reset_config.spi_config.chip_select_pin = chip_select_pin;
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driver->spi_dc_reset_config.spi_config.divisor = spi_divisor;
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driver->spi_dc_reset_config.spi_config.lsb_first = false;
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driver->spi_dc_reset_config.spi_config.mode = spi_mode;
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driver->spi_dc_reset_config.dc_pin = dc_pin;
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driver->spi_dc_reset_config.reset_pin = reset_pin;
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driver->spi_dc_reset_config.command_params_uses_command_pin = false;
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if (!qp_internal_register_device((painter_device_t)driver)) {
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memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
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return NULL;
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}
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return (painter_device_t)driver;
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}
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}
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return NULL;
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}
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#endif // QUANTUM_PAINTER_GC9107_SPI_ENABLE
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37
drivers/painter/gc9xxx/qp_gc9107.h
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37
drivers/painter/gc9xxx/qp_gc9107.h
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// Copyright 2024 Fernando Birra (@gr1mr3aver)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "gpio.h"
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#include "qp_internal.h"
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Quantum Painter GC9107 configurables (add to your keyboard's config.h)
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#ifndef GC9107_NUM_DEVICES
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/**
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* @def This controls the maximum number of GC9107 devices that Quantum Painter can communicate with at any one time.
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* Increasing this number allows for multiple displays to be used.
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*/
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# define GC9107_NUM_DEVICES 1
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#endif
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Quantum Painter GC9107 device factories
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#ifdef QUANTUM_PAINTER_GC9107_SPI_ENABLE
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/**
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* Factory method for an GC9107 SPI LCD device.
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*
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* @param panel_width[in] the width of the display panel
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* @param panel_height[in] the height of the display panel
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* @param chip_select_pin[in] the GPIO pin used for SPI chip select
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* @param dc_pin[in] the GPIO pin used for D/C control
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* @param reset_pin[in] the GPIO pin used for RST
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* @param spi_divisor[in] the SPI divisor to use when communicating with the display
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* @param spi_mode[in] the SPI mode to use when communicating with the display
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* @return the device handle used with all drawing routines in Quantum Painter
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*/
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painter_device_t qp_gc9107_make_spi_device(uint16_t panel_width, uint16_t panel_height, pin_t chip_select_pin, pin_t dc_pin, pin_t reset_pin, uint16_t spi_divisor, int spi_mode);
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#endif // QUANTUM_PAINTER_GC9107_SPI_ENABLE
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135
drivers/painter/gc9xxx/qp_gc9107_opcodes.h
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135
drivers/painter/gc9xxx/qp_gc9107_opcodes.h
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// Copyright 2024 Fernando Birra
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Quantum Painter GC9107 command opcodes
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#define GC9107_GET_POWER_MODE 0x0A // Get power mode
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#define GC9107_GET_MADCTL 0x0B // Get MADCTL
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#define GC9107_GET_PIXEL_FMT 0x0C // Get pixel format
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#define GC9107_GET_IMAGE_FMT 0x0D // Get image format
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#define GC9107_GET_SIGNAL_MODE 0x0E // Get signal mode
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#define GC9107_GET_DIAG_RESULT 0x0F // Get self-diagnostic results
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#define GC9107_SET_FRAME_RATE 0xA8 // Set frame rate
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#define GC9107_SET_COMPLEMENT_RGB 0xAC // Set complement Principle RGB
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#define GC9107_SET_BLANK_PORCH 0xAD // Set blank porch control, 0;front_porch[6:0],0;back_porch[6:0]
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#define GC9107_SET_FUNCTION_CTL1 0xB1 // Set access to AVDD_VCL_CLK and VGH_VGL_CLK commands
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#define GC9107_SET_FUNCTION_CTL2 0xB2 // Set access to VGH, VGH control commands
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#define GC9107_SET_FUNCTION_CTL3 0xB3 // Set access to Gamma control commands
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#define GC9107_SET_DISPLAY_INVERSION 0xB4 // Set Display Inversion control
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#define GC9107_SET_FUNCTION_CTL6 0xB6 // Set access to commands SET_FRAME_RATE, SET_COMPLEMENT_RGB and SET_BLANK_PORCH
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#define GC9107_SET_CUSTOM_ID_INFO 0xD3 // Set customized display id information
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#define GC9107_AVDD_VCL_CLK 0xE3 // AVDD_CLK
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#define GC9107_SET_VGH 0xE8 // Set VGH
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#define GC9107_SET_VGL 0xE9 // Set VGL
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#define GC9107_SET_VGH_VGL_CLK 0xEA // Set VGH and VGL clock divisors
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// GC9107 Parameter constants
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// Parameter values for
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// GC9107_SET_PIXEL_FORMAT
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#define GC9107_PIXEL_FORMAT_12_BPP_IFPF (0b001 << 0) // 12 bits per pixel
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#define GC9107_PIXEL_FORMAT_16_BPP_IFPF (0b101 << 0) // 16 bits per pixel
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#define GC9107_PIXEL_FORMAT_18_BPP_IFPB (0b110 << 0) // 18 bits per pixel
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// Parameter values for
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// GC9107_SET_COMPLEMENT_RGB
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#define GC9107_COMPLEMENT_WITH_0 0x00 // R0 <- B0 <- 0, except if data is FFh
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#define GC9107_COMPLEMENT_WITH_1 0x40 // R0 <- B0 <- 1, except if data is 00h
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#define GC9107_COMPLEMENT_WITH_MSB 0x80 // R0 <- R5, B0 <- B5
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#define GC9107_COMPLEMENT_WITH_LSB 0xC0 // R0 <- B0 <- G0
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// Parameter masks for
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// GC9107_SET_FUNCTION_CTL1
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#define GC9107_ALLOW_AVDD_VCL_CLK 0b00001000 // Allow AVDD_VCL_CLK command
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// Parameter masks for
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// GC9107_SET_FUNCTION_CTL2
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#define GC9107_ALLOW_SET_VGH 0b00000001 // Allow GC9107_SET_VGH
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#define GC9107_ALLOW_SET_VGL 0b00000010 // Allow GC9107_SET_VGL
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#define GC9107_ALLOW_SET_VGH_VGL_CLK 0b00000100 // Allow GC9107_SET_VGH_VGL_CLK
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// Parameter masks for
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// GC9107_SET_FUNCTION_CTL3
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#define GC9107_ALLOW_SET_GAMMA1 0b00000001 // Allow GC9107_SET_GAMMA1
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#define GC9107_ALLOW_SET_GAMMA2 0b00000010 // Allow GC9107_SET_GAMMA2
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// Parameter mask for
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// GC9107_SET_FUNCTION_CTL6
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#define GC9107_ALLOW_SET_FRAMERATE 0b000000001 // Allow GC9107_SET_FRAME_RATE
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#define GC9107_ALLOW_SET_COMPLEMENT_RGB 0b000010000 // Allow GC9107_SET_COMPLEMENT_RGB
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#define GC9107_ALLOW_SET_BLANK_PORCH 0b000100000 // Allow GFC9107_SET_BLANK_PORCH
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// Parameter values for
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// AVDD_CLK_AD part (Most significant nibble)
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#define GC9107_AVDD_CLK_AD_2T 0x00
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#define GC9107_AVDD_CLK_AD_3T 0x10
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#define GC9107_AVDD_CLK_AD_4T 0x20
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#define GC9107_AVDD_CLK_AD_5T 0x30
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#define GC9107_AVDD_CLK_AD_6T 0x40
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#define GC9107_AVDD_CLK_AD_7T 0x50
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#define GC9107_AVDD_CLK_AD_8T 0x60
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#define GC9107_AVDD_CLK_AD_9T 0x70
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// Parameter values for
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// VCL_CLK_AD part (Least significant nibble)
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#define GC9107_VCL_CLK_AD_2T 0x00
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#define GC9107_VCL_CLK_AD_3T 0x01
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#define GC9107_VCL_CLK_AD_4T 0x02
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#define GC9107_VCL_CLK_AD_5T 0x03
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#define GC9107_VCL_CLK_AD_6T 0x04
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#define GC9107_VCL_CLK_AD_7T 0x05
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#define GC9107_VCL_CLK_AD_8T 0x06
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#define GC9107_VCL_CLK_AD_9T 0x07
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// Parameter values for
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// GC9107_SET_VGH
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#define GC9107_VGH_P100 0x20 // +10 V
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#define GC9107_VGH_P110 0x21 // +11 V
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#define GC9107_VGH_P120 0x22 // +12 V
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#define GC9107_VGH_P130 0x23 // +13 V
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#define GC9107_VGH_P140 0x24 // +14 V
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#define GC9107_VGH_P150 0x25 // +15 V
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// Parameter values for
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// GC9107_SET_VGL
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#define VGL_N_075 0x40 // -7.5 V
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#define VGL_N_085 0x41 // -8.5 V
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#define VGL_N_095 0x42 // -9.5 V
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#define VGL_N_100 0x43 // -10.0 V
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#define VGL_N_105 0x44 // -10.5 V
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#define VGL_N_110 0x45 // -11.0 V
|
||||
#define VGL_N_120 0x46 // -12.0 V
|
||||
#define VGL_N_130 0x47 // -13.0 V
|
||||
// Parameter masks for
|
||||
// GC9107_SET_VGH_VGL_CLK (VGH Divisor)
|
||||
#define GC9107_VGH_CLK_DIV_2 0x00 // Clock divisor = 2 -> 6.0 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_3 0x10 // Clock divisor = 3 -> 4.0 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_4 0x20 // Clock divisor = 4 -> 3.0 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_5 0x30 // Clock divisor = 5 -> 2.4 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_6 0x40 // Clock divisor = 6 -> 2.0 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_7 0x50 // Clock divisor = 7 -> 1.7 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_8 0x60 // Clock divisor = 8 -> 1.5 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_9 0x70 // Clock divisor = 9 -> 1.3 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_10 0x80 // Clock divisor = 10 -> 1.2 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_12 0x90 // Clock divisor = 12 -> 1.0 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_15 0xA0 // Clock divisor = 15 -> 0.8 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_20 0xB0 // Clock divisor = 20 -> 0.6 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_24 0xC0 // Clock divisor = 24 -> 0.5 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_30 0xD0 // Clock divisor = 30 -> 0.4 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_40 0xE0 // Clock divisor = 40 -> 0.3 Mhz
|
||||
#define GC9107_VGH_CLK_DIV_60 0xE0 // Clock divisor = 40 -> 0.2 Mhz
|
||||
// Parameter masks for
|
||||
// GC9107_SET_VGH_VGL_CLK (VGL Divisor)
|
||||
#define GC9107_VGL_CLK_DIV_2 0x00 // Clock divisor = 2 -> 6.0 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_3 0x01 // Clock divisor = 3 -> 4.0 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_4 0x02 // Clock divisor = 4 -> 3.0 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_5 0x03 // Clock divisor = 5 -> 2.4 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_6 0x04 // Clock divisor = 6 -> 2.0 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_7 0x05 // Clock divisor = 7 -> 1.7 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_8 0x06 // Clock divisor = 8 -> 1.5 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_9 0x07 // Clock divisor = 9 -> 1.3 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_10 0x08 // Clock divisor = 10 -> 1.2 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_12 0x09 // Clock divisor = 12 -> 1.0 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_15 0x0A // Clock divisor = 15 -> 0.8 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_20 0x0B // Clock divisor = 20 -> 0.6 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_24 0x0C // Clock divisor = 24 -> 0.5 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_30 0x0D // Clock divisor = 30 -> 0.4 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_40 0x0E // Clock divisor = 40 -> 0.3 Mhz
|
||||
#define GC9107_VGL_CLK_DIV_60 0x0E // Clock divisor = 40 -> 0.2 Mhz
|
||||
|
|
@ -5,6 +5,7 @@
|
|||
#include "qp_internal.h"
|
||||
#include "qp_comms.h"
|
||||
#include "qp_gc9a01.h"
|
||||
#include "qp_gc9xxx_opcodes.h"
|
||||
#include "qp_gc9a01_opcodes.h"
|
||||
#include "qp_tft_panel.h"
|
||||
|
||||
|
|
@ -20,71 +21,40 @@ tft_panel_dc_reset_painter_device_t gc9a01_drivers[GC9A01_NUM_DEVICES] = {0};
|
|||
__attribute__((weak)) bool qp_gc9a01_init(painter_device_t device, painter_rotation_t rotation) {
|
||||
// A lot of these "unknown" opcodes are sourced from other OSS projects and are seemingly required for this display to function.
|
||||
// clang-format off
|
||||
|
||||
const uint8_t gc9a01_init_sequence[] = {
|
||||
// Command, Delay, N, Data[N]
|
||||
GC9A01_SET_INTER_REG_ENABLE2, 0, 0,
|
||||
0xEB, 0, 1, 0x14,
|
||||
GC9A01_SET_INTER_REG_ENABLE1, 0, 0,
|
||||
GC9A01_SET_INTER_REG_ENABLE2, 0, 0,
|
||||
0xEB, 0, 1, 0x14,
|
||||
GC9XXX_SET_INTER_REG_ENABLE1, 0, 0,
|
||||
GC9XXX_SET_INTER_REG_ENABLE2, 0, 0,
|
||||
0x84, 0, 1, 0x40,
|
||||
0x85, 0, 1, 0xFF,
|
||||
0x86, 0, 1, 0xFF,
|
||||
0x87, 0, 1, 0xFF,
|
||||
0x88, 0, 1, 0x0A,
|
||||
0x89, 0, 1, 0x21,
|
||||
0x8a, 0, 1, 0x00,
|
||||
0x8b, 0, 1, 0x80,
|
||||
0x8c, 0, 1, 0x01,
|
||||
0x8d, 0, 1, 0x01,
|
||||
0x8e, 0, 1, 0xFF,
|
||||
0x8f, 0, 1, 0xFF,
|
||||
GC9A01_SET_FUNCTION_CTL, 0, 2, 0x00, 0x20,
|
||||
GC9A01_SET_PIX_FMT, 0, 1, 0x55,
|
||||
0x90, 0, 4, 0x08, 0x08, 0x08, 0x08,
|
||||
0xBD, 0, 1, 0x06,
|
||||
0xBC, 0, 1, 0x00,
|
||||
0xFF, 0, 3, 0x60, 0x01, 0x04,
|
||||
GC9A01_SET_POWER_CTL_2, 0, 1, 0x13,
|
||||
GC9A01_SET_POWER_CTL_3, 0, 1, 0x13,
|
||||
GC9A01_SET_FUNCTION_CTL, 0, 3, 0x00, GC9A01_SOURCE_OUTPUT_SCAN_DIRECTION_S360_TO_S1 | GC9A01_GATE_OUTPUT_SCAN_DIRECTION_G1_TO_G32, GC9A01_LCD_DRIVE_LINE_240, // Only works if the previous command is present (undocumented)
|
||||
GC9A01_SET_POWER_CTL_2, 0, 1, 0x20,
|
||||
GC9A01_SET_POWER_CTL_3, 0, 1, 0x20,
|
||||
GC9A01_SET_POWER_CTL_4, 0, 1, 0x22,
|
||||
0xBE, 0, 1, 0x11,
|
||||
0xE1, 0, 2, 0x10, 0x0E,
|
||||
0xDF, 0, 3, 0x21, 0x0C, 0x02,
|
||||
GC9A01_SET_GAMMA1, 0, 6, 0x45, 0x09, 0x08, 0x08, 0x26, 0x2A,
|
||||
GC9A01_SET_GAMMA2, 0, 6, 0x43, 0x70, 0x72, 0x36, 0x37, 0x6F,
|
||||
GC9XXX_SET_GAMMA1, 0, 6, 0x45, 0x09, 0x08, 0x08, 0x26, 0x2A,
|
||||
GC9XXX_SET_GAMMA2, 0, 6, 0x43, 0x70, 0x72, 0x36, 0x37, 0x6F,
|
||||
GC9A01_SET_GAMMA3, 0, 6, 0x45, 0x09, 0x08, 0x08, 0x26, 0x2A,
|
||||
GC9A01_SET_GAMMA4, 0, 6, 0x43, 0x70, 0x72, 0x36, 0x37, 0x6F,
|
||||
0xED, 0, 2, 0x1B, 0x0B,
|
||||
0xAE, 0, 1, 0x77,
|
||||
0xCD, 0, 1, 0x63,
|
||||
0x70, 0, 9, 0x07, 0x07, 0x04, 0x0E, 0x0F, 0x09, 0x07, 0x08, 0x03,
|
||||
GC9A01_SET_FRAME_RATE, 0, 1, 0x34,
|
||||
0x62, 0, 12, 0x18, 0x0D, 0x71, 0xED, 0x70, 0x70, 0x18, 0x0F, 0x71, 0xEF, 0x70, 0x70,
|
||||
0x63, 0, 12, 0x18, 0x11, 0x71, 0xF1, 0x70, 0x70, 0x18, 0x13, 0x71, 0xF3, 0x70, 0x70,
|
||||
0x64, 0, 7, 0x28, 0x29, 0xF1, 0x01, 0xF1, 0x00, 0x07,
|
||||
0x66, 0, 10, 0x3C, 0x00, 0xCD, 0x67, 0x45, 0x45, 0x10, 0x00, 0x00, 0x00,
|
||||
0x67, 0, 10, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0x54, 0x10, 0x32, 0x98,
|
||||
0x74, 0, 7, 0x10, 0x85, 0x80, 0x00, 0x00, 0x4E, 0x00,
|
||||
0x98, 0, 2, 0x3E, 0x07,
|
||||
GC9A01_CMD_TEARING_OFF, 0, 0,
|
||||
GC9A01_CMD_INVERT_OFF, 0, 0,
|
||||
GC9A01_CMD_SLEEP_OFF, 120, 0,
|
||||
GC9A01_CMD_DISPLAY_ON, 20, 0
|
||||
GC9XXX_CMD_TEARING_ON, 0, 0,
|
||||
GC9XXX_SET_PIXEL_FORMAT, 0, 1, GC9A01_PIXEL_FORMAT_16_BPP_DBI,
|
||||
GC9XXX_CMD_INVERT_ON, 0, 0,
|
||||
GC9XXX_CMD_SLEEP_OFF, 120, 0,
|
||||
GC9XXX_CMD_DISPLAY_ON, 20, 0
|
||||
};
|
||||
// clang-format on
|
||||
|
||||
// clang-format on
|
||||
qp_comms_bulk_command_sequence(device, gc9a01_init_sequence, sizeof(gc9a01_init_sequence));
|
||||
|
||||
// Configure the rotation (i.e. the ordering and direction of memory writes in GRAM)
|
||||
const uint8_t madctl[] = {
|
||||
[QP_ROTATION_0] = GC9A01_MADCTL_BGR,
|
||||
[QP_ROTATION_90] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MX | GC9A01_MADCTL_MV,
|
||||
[QP_ROTATION_180] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MX | GC9A01_MADCTL_MY,
|
||||
[QP_ROTATION_270] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MV | GC9A01_MADCTL_MY,
|
||||
[QP_ROTATION_0] = GC9XXX_MADCTL_BGR,
|
||||
[QP_ROTATION_90] = GC9XXX_MADCTL_BGR | GC9XXX_MADCTL_MX | GC9XXX_MADCTL_MV,
|
||||
[QP_ROTATION_180] = GC9XXX_MADCTL_BGR | GC9XXX_MADCTL_MX | GC9XXX_MADCTL_MY,
|
||||
[QP_ROTATION_270] = GC9XXX_MADCTL_BGR | GC9XXX_MADCTL_MV | GC9XXX_MADCTL_MY,
|
||||
};
|
||||
qp_comms_command_databyte(device, GC9A01_SET_MEM_ACS_CTL, madctl[rotation]);
|
||||
qp_comms_command_databyte(device, GC9XXX_SET_MEM_ACS_CTL, madctl[rotation]);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -110,11 +80,11 @@ const tft_panel_dc_reset_painter_driver_vtable_t gc9a01_driver_vtable = {
|
|||
.swap_window_coords = false,
|
||||
.opcodes =
|
||||
{
|
||||
.display_on = GC9A01_CMD_DISPLAY_ON,
|
||||
.display_off = GC9A01_CMD_DISPLAY_OFF,
|
||||
.set_column_address = GC9A01_SET_COL_ADDR,
|
||||
.set_row_address = GC9A01_SET_PAGE_ADDR,
|
||||
.enable_writes = GC9A01_SET_MEM,
|
||||
.display_on = GC9XXX_CMD_DISPLAY_ON,
|
||||
.display_off = GC9XXX_CMD_DISPLAY_OFF,
|
||||
.set_column_address = GC9XXX_SET_COL_ADDR,
|
||||
.set_row_address = GC9XXX_SET_ROW_ADDR,
|
||||
.enable_writes = GC9XXX_SET_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
104
drivers/painter/gc9xxx/qp_gc9a01_opcodes.h
Normal file
104
drivers/painter/gc9xxx/qp_gc9a01_opcodes.h
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
// Copyright 2021 Paul Cotter (@gr1mr3aver)
|
||||
// Copyright 2024 Fernando Birra
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
#pragma once
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Quantum Painter GC9A01 command opcodes
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define GC9A01_SET_MEM_CONT 0x3C // Set memory continue
|
||||
#define GC9A01_SET_BRIGHTNESS 0x51 // Set brightness
|
||||
#define GC9A01_SET_DISPLAY_CTL 0x53 // Set display ctl
|
||||
|
||||
#define GC9A01_SET_RGB_IF_SIG_CTL 0xB0 // RGB IF signal ctl
|
||||
#define GC9A01_SET_BLANKING_PORCH_CTL 0xB5 // Set blanking porch ctl
|
||||
#define GC9A01_SET_FUNCTION_CTL 0xB6 // Set function ctl
|
||||
#define GC9A01_SET_TEARING_EFFECT 0xBA // Set tering effect control
|
||||
#define GC9A01_SET_POWER_CTL_7 0xA7 // Set power ctl 7
|
||||
#define GC9A01_SET_POWER_CTL_1 0xC1 // Set power ctl 1
|
||||
#define GC9A01_SET_POWER_CTL_2 0xC3 // Set power ctl 2
|
||||
#define GC9A01_SET_POWER_CTL_3 0xC4 // Set power ctl 3
|
||||
#define GC9A01_SET_POWER_CTL_4 0xC9 // Set power ctl 4
|
||||
#define GC9A01_SET_FRAME_RATE 0xE8 // Set frame rate
|
||||
#define GC9A01_SET_SPI_2DATA 0xE9 // Set frame rate
|
||||
#define GC9A01_SET_GAMMA3 0xF2 // Set gamma 3
|
||||
#define GC9A01_SET_GAMMA4 0xF3 // Set gamma 4
|
||||
#define GC9A01_SET_IF_CTL 0xF6 // Set interface control
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// GC9A01 MADCTL Flags
|
||||
#define GC9A01_MADCTL_MH 0b00000100
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// GC9A01 Parameter constants
|
||||
|
||||
// Parameter values for
|
||||
// GC9A01_SET_PIXEL_FORMAT
|
||||
#define GC9A01_PIXEL_FORMAT_12_BPP_DBI (0b011 << 0) // 12 bits/pixel MCU interface format
|
||||
#define GC9A01_PIXEL_FORMAT_16_BPP_DBI (0b101 << 0) // 16 bits/pixel MCU interface format
|
||||
#define GC9A01_PIXEL_FORMAT_18_BPP_DBI (0b110 << 0) // 18 bits/pixel MCU interface format
|
||||
#define GC9A01_PIXEL_FORMAT_16_BPP_DPI (0b101 << 4) // 16 bits/pixel RGB interface format
|
||||
#define GC9A01_PIXEL_FORMAT_18_BPP_DPI (0b110 << 4) // 18 bits/pixel RGB interface format
|
||||
|
||||
// Parameter values for
|
||||
// GC9A01_SET_FUNCTION_CTL (2nd parameter)
|
||||
#define GC9A01_SOURCE_OUTPUT_SCAN_DIRECTION_S1_TO_S360 0b00000000
|
||||
#define GC9A01_SOURCE_OUTPUT_SCAN_DIRECTION_S360_TO_S1 0b00100000
|
||||
#define GC9A01_GATE_OUTPUT_SCAN_DIRECTION_G1_TO_G32 0b00000000
|
||||
#define GC9A01_GATE_OUTPUT_SCAN_DIRECTION_G32_TO_G1 0b01000000
|
||||
#define GC9A01_SCAN_MODE_INTER 0x10
|
||||
|
||||
// Parameter values for
|
||||
// GC9A01_SET_FUNCTION_CTL (3rd parameter)
|
||||
#define GC9A01_LCD_DRIVE_LINE_16 0x01
|
||||
#define GC9A01_LCD_DRIVE_LINE_24 0x02
|
||||
#define GC9A01_LCD_DRIVE_LINE_32 0x03
|
||||
#define GC9A01_LCD_DRIVE_LINE_40 0x04
|
||||
#define GC9A01_LCD_DRIVE_LINE_48 0x05
|
||||
#define GC9A01_LCD_DRIVE_LINE_56 0x06
|
||||
#define GC9A01_LCD_DRIVE_LINE_64 0x07
|
||||
#define GC9A01_LCD_DRIVE_LINE_72 0x08
|
||||
#define GC9A01_LCD_DRIVE_LINE_80 0x09
|
||||
#define GC9A01_LCD_DRIVE_LINE_88 0x0A
|
||||
#define GC9A01_LCD_DRIVE_LINE_96 0x0B
|
||||
#define GC9A01_LCD_DRIVE_LINE_104 0x0C
|
||||
#define GC9A01_LCD_DRIVE_LINE_112 0x0D
|
||||
#define GC9A01_LCD_DRIVE_LINE_120 0x0E
|
||||
#define GC9A01_LCD_DRIVE_LINE_128 0x0F
|
||||
#define GC9A01_LCD_DRIVE_LINE_136 0x10
|
||||
#define GC9A01_LCD_DRIVE_LINE_144 0x11
|
||||
#define GC9A01_LCD_DRIVE_LINE_152 0x12
|
||||
#define GC9A01_LCD_DRIVE_LINE_160 0x13
|
||||
#define GC9A01_LCD_DRIVE_LINE_168 0x14
|
||||
#define GC9A01_LCD_DRIVE_LINE_176 0x15
|
||||
#define GC9A01_LCD_DRIVE_LINE_184 0x16
|
||||
#define GC9A01_LCD_DRIVE_LINE_192 0x17
|
||||
#define GC9A01_LCD_DRIVE_LINE_200 0x18
|
||||
#define GC9A01_LCD_DRIVE_LINE_208 0x19
|
||||
#define GC9A01_LCD_DRIVE_LINE_216 0x1A
|
||||
#define GC9A01_LCD_DRIVE_LINE_224 0x1B
|
||||
#define GC9A01_LCD_DRIVE_LINE_232 0x1C
|
||||
#define GC9A01_LCD_DRIVE_LINE_240 0x1D
|
||||
|
||||
// Parameter values for
|
||||
// GC9A01_SET_DISPLAY_CTL
|
||||
#define GC9A01_BRIGHTNESS_CONTROL_ON 0b00100000
|
||||
#define GC9A01_DIMMING_ON 0b00001000
|
||||
#define GC9A01_BACKLIGHT_ON 0b00000100
|
||||
#define GC9A01_BRIGHTNESS_CONTROL_OFF 0b00000000
|
||||
#define GC9A01_DIMMING_OFF 0b00000000
|
||||
#define GC9A01_BACKLIGHT_OFF 0b00000000
|
||||
|
||||
// Parameter values for
|
||||
// GC9A01_SET_IF_CTL
|
||||
#define GC9A01_DISPLAY_MODE_INTERNAL_CLOCK 0b00000000
|
||||
#define GC9A01_DISPLAY_MODE_RGB_INTERFACE 0b00000100
|
||||
#define GC9A01_DISPLAY_MODE_VSYNC_INTERFACE 0b00001000
|
||||
#define GC9A01_DSISPLAY_MODE_DISABLED 0b00001100
|
||||
|
||||
#define GC0A01_GRAM_INTERFACE_VSYNC 0b00000000
|
||||
#define GC9A01_GRAM_INTERFACE_RGB 0b00000010
|
||||
|
||||
#define GC9A01_RGB_INTERFACE_MODE_1_TRANSFER 0b00000000
|
||||
#define GC9A01_RGB_INTERFACE_MODE_3_TRANSFER 0b00000001
|
||||
55
drivers/painter/gc9xxx/qp_gc9xxx_opcodes.h
Normal file
55
drivers/painter/gc9xxx/qp_gc9xxx_opcodes.h
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
// Copyright 2021 Paul Cotter (@gr1mr3aver)
|
||||
// Copyright 2024 Fernando Birra
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
#pragma once
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Quantum Painter GC9xxx command opcodes
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define GC9XXX_GET_ID_INFO 0x04 // Get ID information
|
||||
#define GC9XXX_GET_STATUS 0x09 // Get status
|
||||
|
||||
#define GC9XXX_CMD_SLEEP_ON 0x10 // Enter sleep mode
|
||||
#define GC9XXX_CMD_SLEEP_OFF 0x11 // Exit sleep mode
|
||||
#define GC9XXX_CMD_PARTIAL_ON 0x12 // Enter partial mode
|
||||
#define GC9XXX_CMD_PARTIAL_OFF 0x13 // Exit partial mode
|
||||
|
||||
#define GC9XXX_CMD_INVERT_OFF 0x20 // Exit inverted mode
|
||||
#define GC9XXX_CMD_INVERT_ON 0x21 // Enter inverted mode
|
||||
#define GC9XXX_CMD_DISPLAY_OFF 0x28 // Disable display
|
||||
#define GC9XXX_CMD_DISPLAY_ON 0x29 // Enable display
|
||||
#define GC9XXX_SET_COL_ADDR 0x2A // Set column address (MSB(StartCol),LSB(StartCol),MSB(EndCol),LSB(EndCol)
|
||||
#define GC9XXX_SET_ROW_ADDR 0x2B // Set row address (MSB(StartRow),LSB(StartRow),MSB(EndRow),LSB(EndRow)
|
||||
#define GC9XXX_SET_MEM 0x2C // Set (write) memory
|
||||
|
||||
#define GC9XXX_SET_PARTIAL_AREA 0x30 // Set partial area (MSB(StartRow),LSB(StartRow),MSB(EndRow),LSB(EndRow)
|
||||
#define GC9XXX_SET_VSCROLL 0x33 // Set vertical scroll MSB(TFA),LSB(TFA),MSB(VSA),LSB(VSA)+ GC9107 extra param: MSB(BFA),LSB(BFA)
|
||||
#define GC9XXX_CMD_TEARING_OFF 0x34 // Tearing effect line OFF
|
||||
#define GC9XXX_CMD_TEARING_ON 0x35 // Tearing effect line ON
|
||||
#define GC9XXX_SET_MEM_ACS_CTL 0x36 // Set mem access ctl
|
||||
#define GC9XXX_SET_VSCROLL_ADDR 0x37 // Set vscroll start addr
|
||||
#define GC9XXX_CMD_IDLE_OFF 0x38 // Exit idle mode
|
||||
#define GC9XXX_CMD_IDLE_ON 0x39 // Enter idle mode
|
||||
#define GC9XXX_SET_PIXEL_FORMAT 0x3A // Set pixel format
|
||||
#define GC9XXX_SET_TEAR_SCANLINE 0x44 // Set tearing scanline (Scanline = LS bit of Param 1 (GC9A01) + Param 2(GC9XXX))
|
||||
#define GC9XXX_GET_TEAR_SCANLINE 0x45 // Get tearing scanline (Scanline = LS bit of Param 1 (GC9A01) + Param 2(GC9XXX))
|
||||
#define GC9XXX_GET_ID1 0xDA // Get ID1
|
||||
#define GC9XXX_GET_ID2 0xDB // Get ID2
|
||||
#define GC9XXX_GET_ID3 0xDC // Get ID3
|
||||
#define GC9XXX_SET_INTER_REG_ENABLE1 0xFE // Enable Inter Register 1
|
||||
#define GC9XXX_SET_INTER_REG_ENABLE2 0xEF // Enable Inter Register 2
|
||||
#define GC9XXX_SET_GAMMA1 0xF0 // Set gamma 1
|
||||
#define GC9XXX_SET_GAMMA2 0xF1 // Set gamma 2
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// MADCTL Flags
|
||||
#define GC9XXX_MADCTL_MY 0b10000000 // Mirror Y (row address order)
|
||||
#define GC9XXX_MADCTL_MX 0b01000000 // Mirror X (column address order)
|
||||
#define GC9XXX_MADCTL_MV 0b00100000 // Vertical Refresh Order (bottom to top)
|
||||
#define GC9XXX_MADCTL_ML 0b00010000
|
||||
#define GC9XXX_MADCTL_BGR 0b00001000
|
||||
#define GC9XXX_MADCTL_RGB 0b00000000
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// GC9XXX Parameter constants
|
||||
|
|
@ -539,6 +539,12 @@ int16_t qp_drawtext_recolor(painter_device_t device, uint16_t x, uint16_t y, pai
|
|||
# define GC9A01_NUM_DEVICES 0
|
||||
#endif // QUANTUM_PAINTER_GC9A01_ENABLE
|
||||
|
||||
#ifdef QUANTUM_PAINTER_GC9107_ENABLE
|
||||
# include "qp_gc9107.h"
|
||||
#else // QUANTUM_PAINTER_GC9107_ENABLE
|
||||
# define GC9107_NUM_DEVICES 0
|
||||
#endif // QUANTUM_PAINTER_GC9107_ENABLE
|
||||
|
||||
#ifdef QUANTUM_PAINTER_SSD1351_ENABLE
|
||||
# include "qp_ssd1351.h"
|
||||
#else // QUANTUM_PAINTER_SSD1351_ENABLE
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ enum {
|
|||
+ (ST7789_NUM_DEVICES) // ST7789
|
||||
+ (ST7735_NUM_DEVICES) // ST7735
|
||||
+ (GC9A01_NUM_DEVICES) // GC9A01
|
||||
+ (GC9107_NUM_DEVICES) // GC9107
|
||||
+ (SSD1351_NUM_DEVICES) // SSD1351
|
||||
+ (SH1106_NUM_DEVICES) // SH1106
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ VALID_QUANTUM_PAINTER_DRIVERS := \
|
|||
st7735_spi \
|
||||
st7789_spi \
|
||||
gc9a01_spi \
|
||||
gc9107_spi \
|
||||
ssd1351_spi \
|
||||
sh1106_i2c \
|
||||
sh1106_spi
|
||||
|
|
@ -131,10 +132,21 @@ define handle_quantum_painter_driver
|
|||
OPT_DEFS += -DQUANTUM_PAINTER_GC9A01_ENABLE -DQUANTUM_PAINTER_GC9A01_SPI_ENABLE
|
||||
COMMON_VPATH += \
|
||||
$(DRIVER_PATH)/painter/tft_panel \
|
||||
$(DRIVER_PATH)/painter/gc9a01
|
||||
$(DRIVER_PATH)/painter/gc9xxx
|
||||
SRC += \
|
||||
$(DRIVER_PATH)/painter/tft_panel/qp_tft_panel.c \
|
||||
$(DRIVER_PATH)/painter/gc9a01/qp_gc9a01.c
|
||||
$(DRIVER_PATH)/painter/gc9xxx/qp_gc9a01.c
|
||||
|
||||
else ifeq ($$(strip $$(CURRENT_PAINTER_DRIVER)),gc9107_spi)
|
||||
QUANTUM_PAINTER_NEEDS_COMMS_SPI := yes
|
||||
QUANTUM_PAINTER_NEEDS_COMMS_SPI_DC_RESET := yes
|
||||
OPT_DEFS += -DQUANTUM_PAINTER_GC9107_ENABLE -DQUANTUM_PAINTER_GC9107_SPI_ENABLE
|
||||
COMMON_VPATH += \
|
||||
$(DRIVER_PATH)/painter/tft_panel \
|
||||
$(DRIVER_PATH)/painter/gc9xxx
|
||||
SRC += \
|
||||
$(DRIVER_PATH)/painter/tft_panel/qp_tft_panel.c \
|
||||
$(DRIVER_PATH)/painter/gc9xxx/qp_gc9107.c
|
||||
|
||||
else ifeq ($$(strip $$(CURRENT_PAINTER_DRIVER)),ssd1351_spi)
|
||||
QUANTUM_PAINTER_NEEDS_COMMS_SPI := yes
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue