Add non blackpill F4x1 config files (#16600)
* Add non blackpill F4x1 config files * Move ld files * Remove f401 i2c bodges * more bodge? * Update to recommended defaults
This commit is contained in:
Joel Challis
GitHub
parent
45504bb094
commit
a5e810b86c
22 changed files with 713 additions and 41 deletions
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@ -17,4 +17,61 @@
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#include_next "board.h"
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// Force B9 as input to align with qmk defaults
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#undef VAL_GPIOB_MODER
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#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
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PIN_MODE_INPUT(GPIOB_PIN1) | \
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PIN_MODE_INPUT(GPIOB_PIN2) | \
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PIN_MODE_ALTERNATE(GPIOB_SWO) | \
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PIN_MODE_INPUT(GPIOB_PIN4) | \
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PIN_MODE_INPUT(GPIOB_PIN5) | \
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PIN_MODE_INPUT(GPIOB_LSM303DLHC_SCL) | \
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PIN_MODE_INPUT(GPIOB_PIN7) | \
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PIN_MODE_INPUT(GPIOB_PIN8) | \
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PIN_MODE_INPUT(GPIOB_LSM303DLHC_SDA) | \
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PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\
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PIN_MODE_INPUT(GPIOB_PIN11) | \
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PIN_MODE_INPUT(GPIOB_PIN12) | \
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PIN_MODE_INPUT(GPIOB_PIN13) | \
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PIN_MODE_INPUT(GPIOB_PIN14) | \
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PIN_MODE_INPUT(GPIOB_PIN15))
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#undef VAL_GPIOB_PUPDR
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#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
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PIN_PUPDR_PULLUP(GPIOB_SWO) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
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PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SCL) |\
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PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
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PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SDA) |\
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PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\
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PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN15))
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#undef VAL_GPIOB_AFRL
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#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
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PIN_AFIO_AF(GPIOB_SWO, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
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PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 0) | \
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PIN_AFIO_AF(GPIOB_PIN7, 0U))
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#undef VAL_GPIOB_AFRH
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#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
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PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 0) | \
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PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\
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PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN15, 0U))
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#undef STM32_HSE_BYPASS
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@ -0,0 +1,9 @@
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# List of all the board related files.
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY/board.c
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# Required include directories
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BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY
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# Shared variables
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ALLCSRC += $(BOARDSRC)
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ALLINC += $(BOARDINC)
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@ -0,0 +1,77 @@
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/* Copyright 2020 Nick Brassel (tzarc)
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include_next "board.h"
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// Force B9 as input to align with qmk defaults
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#undef VAL_GPIOB_MODER
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#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
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PIN_MODE_INPUT(GPIOB_PIN1) | \
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PIN_MODE_INPUT(GPIOB_PIN2) | \
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PIN_MODE_ALTERNATE(GPIOB_SWO) | \
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PIN_MODE_INPUT(GPIOB_PIN4) | \
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PIN_MODE_INPUT(GPIOB_PIN5) | \
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PIN_MODE_INPUT(GPIOB_LSM303DLHC_SCL) | \
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PIN_MODE_INPUT(GPIOB_PIN7) | \
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PIN_MODE_INPUT(GPIOB_PIN8) | \
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PIN_MODE_INPUT(GPIOB_LSM303DLHC_SDA) | \
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PIN_MODE_ALTERNATE(GPIOB_MP45DT02_CLK_IN) |\
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PIN_MODE_INPUT(GPIOB_PIN11) | \
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PIN_MODE_INPUT(GPIOB_PIN12) | \
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PIN_MODE_INPUT(GPIOB_PIN13) | \
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PIN_MODE_INPUT(GPIOB_PIN14) | \
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PIN_MODE_INPUT(GPIOB_PIN15))
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#undef VAL_GPIOB_PUPDR
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#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
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PIN_PUPDR_PULLUP(GPIOB_SWO) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
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PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SCL) |\
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PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
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PIN_PUPDR_PULLUP(GPIOB_LSM303DLHC_SDA) |\
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PIN_PUPDR_FLOATING(GPIOB_MP45DT02_CLK_IN) |\
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PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
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PIN_PUPDR_PULLUP(GPIOB_PIN15))
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#undef VAL_GPIOB_AFRL
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#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
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PIN_AFIO_AF(GPIOB_SWO, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
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PIN_AFIO_AF(GPIOB_LSM303DLHC_SCL, 0) | \
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PIN_AFIO_AF(GPIOB_PIN7, 0U))
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#undef VAL_GPIOB_AFRH
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#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
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PIN_AFIO_AF(GPIOB_LSM303DLHC_SDA, 0) | \
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PIN_AFIO_AF(GPIOB_MP45DT02_CLK_IN, 5U) |\
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PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
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PIN_AFIO_AF(GPIOB_PIN15, 0U))
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#undef STM32_HSE_BYPASS
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@ -0,0 +1,22 @@
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/* Copyright 2020 Nick Brassel (tzarc)
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#pragma once
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#define BOARD_OTG_NOVBUSSENS 1
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#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
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# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
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#endif
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244
platforms/chibios/boards/GENERIC_STM32_F401XC/configs/mcuconf.h
Normal file
244
platforms/chibios/boards/GENERIC_STM32_F401XC/configs/mcuconf.h
Normal file
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@ -0,0 +1,244 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32F4xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F4xx_MCUCONF
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#define STM32F401_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_CLOCK48_REQUIRED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 4
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#define STM32_PLLN_VALUE 168
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#define STM32_PLLP_VALUE 4
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#define STM32_PLLQ_VALUE 7
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCPRE_VALUE 8
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI16_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 15
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#define STM32_IRQ_EXTI18_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_PRIORITY 6
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#define STM32_IRQ_EXTI21_PRIORITY 15
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#define STM32_IRQ_EXTI22_PRIORITY 15
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#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
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#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
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#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 12
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#define STM32_IRQ_USART2_PRIORITY 12
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#define STM32_IRQ_USART6_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 6
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM9 FALSE
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#define STM32_GPT_USE_TIM10 FALSE
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#define STM32_GPT_USE_TIM11 FALSE
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* I2S driver system settings.
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*/
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#define STM32_I2S_USE_SPI2 FALSE
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#define STM32_I2S_USE_SPI3 FALSE
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#define STM32_I2S_SPI2_IRQ_PRIORITY 10
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#define STM32_I2S_SPI3_IRQ_PRIORITY 10
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#define STM32_I2S_SPI2_DMA_PRIORITY 1
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#define STM32_I2S_SPI3_DMA_PRIORITY 1
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#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_USE_TIM10 FALSE
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#define STM32_ICU_USE_TIM11 FALSE
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM5 FALSE
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#define STM32_PWM_USE_TIM9 FALSE
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#define STM32_PWM_USE_TIM10 FALSE
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#define STM32_PWM_USE_TIM11 FALSE
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_SERIAL_USE_USART6 FALSE
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 8
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART6 FALSE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 TRUE
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION 2
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG FALSE
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
# List of all the board related files.
|
||||
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Copyright 2020 Nick Brassel (tzarc)
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include_next "board.h"
|
||||
|
||||
#undef STM32_HSE_BYPASS
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/* Copyright 2020 Nick Brassel (tzarc)
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#define BOARD_OTG_NOVBUSSENS 1
|
||||
|
||||
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
|
||||
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
|
||||
#endif
|
||||
252
platforms/chibios/boards/GENERIC_STM32_F411XE/configs/mcuconf.h
Normal file
252
platforms/chibios/boards/GENERIC_STM32_F411XE/configs/mcuconf.h
Normal file
|
|
@ -0,0 +1,252 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F4xx_MCUCONF
|
||||
#define STM32F411_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT FALSE
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_BKPRAM_ENABLE FALSE
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#define STM32_CLOCK48_REQUIRED TRUE
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_PLLM_VALUE 4
|
||||
#define STM32_PLLN_VALUE 96
|
||||
#define STM32_PLLP_VALUE 2
|
||||
#define STM32_PLLQ_VALUE 4
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#define STM32_RTCPRE_VALUE 8
|
||||
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
|
||||
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
|
||||
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
|
||||
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
|
||||
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
||||
#define STM32_PLLI2SN_VALUE 192
|
||||
#define STM32_PLLI2SR_VALUE 5
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI1_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI2_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI3_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI4_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI16_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI17_PRIORITY 15
|
||||
#define STM32_IRQ_EXTI18_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI19_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI20_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI21_PRIORITY 15
|
||||
#define STM32_IRQ_EXTI22_PRIORITY 15
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
|
||||
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY 7
|
||||
#define STM32_IRQ_TIM2_PRIORITY 7
|
||||
#define STM32_IRQ_TIM3_PRIORITY 7
|
||||
#define STM32_IRQ_TIM4_PRIORITY 7
|
||||
#define STM32_IRQ_TIM5_PRIORITY 7
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY 12
|
||||
#define STM32_IRQ_USART2_PRIORITY 12
|
||||
#define STM32_IRQ_USART6_PRIORITY 12
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 6
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM5 FALSE
|
||||
#define STM32_GPT_USE_TIM9 FALSE
|
||||
#define STM32_GPT_USE_TIM10 FALSE
|
||||
#define STM32_GPT_USE_TIM11 FALSE
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 FALSE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_USE_I2C3 FALSE
|
||||
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY 3
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI2 FALSE
|
||||
#define STM32_I2S_USE_SPI3 FALSE
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 FALSE
|
||||
#define STM32_ICU_USE_TIM2 FALSE
|
||||
#define STM32_ICU_USE_TIM3 FALSE
|
||||
#define STM32_ICU_USE_TIM4 FALSE
|
||||
#define STM32_ICU_USE_TIM5 FALSE
|
||||
#define STM32_ICU_USE_TIM9 FALSE
|
||||
#define STM32_ICU_USE_TIM10 FALSE
|
||||
#define STM32_ICU_USE_TIM11 FALSE
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_USE_TIM4 FALSE
|
||||
#define STM32_PWM_USE_TIM5 FALSE
|
||||
#define STM32_PWM_USE_TIM9 FALSE
|
||||
#define STM32_PWM_USE_TIM10 FALSE
|
||||
#define STM32_PWM_USE_TIM11 FALSE
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE 32
|
||||
#define STM32_RTC_PRESS_VALUE 1024
|
||||
#define STM32_RTC_CR_INIT 0
|
||||
#define STM32_RTC_TAMPCR_INIT 0
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 FALSE
|
||||
#define STM32_SERIAL_USE_USART2 FALSE
|
||||
#define STM32_SERIAL_USE_USART6 FALSE
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 FALSE
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 8
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART6 FALSE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 TRUE
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION 2
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG FALSE
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue