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Software PDI mode breaks unless the software USART has 100 cycles between bits.

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This commit is contained in:
Dean Camera 2010-03-17 11:48:39 +00:00
parent 7d51e51c79
commit 9a5ae36a4f
8 changed files with 20 additions and 22 deletions
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12
Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
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@ -162,7 +162,7 @@ void XPROGTarget_EnableTargetPDI(void)
/* Set up the synchronous USART for XMEGA communications -
8 data bits, even parity, 2 stop bits */
UBRR1 = (F_CPU / 500000UL);
UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);
UCSR1B = (1 << TXEN1);
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
#else
@ -203,7 +203,7 @@ void XPROGTarget_EnableTargetTPI(void)
/* Set up the synchronous USART for TINY communications -
8 data bits, even parity, 2 stop bits */
UBRR1 = (F_CPU / 500000UL);
UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);
UCSR1B = (1 << TXEN1);
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
#else
@ -239,16 +239,18 @@ void XPROGTarget_DisableTargetPDI(void)
/* Tristate all pins */
DDRD &= ~((1 << 5) | (1 << 3));
PORTD &= ~((1 << 3) | (1 << 2));
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
#else
/* Turn off software USART management timer */
TCCR1B = 0;
/* Tristate all pins */
/* Set DATA and CLOCK lines to inputs */
BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;
BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
/* Tristate DATA and CLOCK lines */
BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
#endif
}