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DC01 keyboard addition (#3428)

Browse source 
* DC01 initial commit

- Addition of directories
- Left readme

* Initial commit of left half

* Initial files for right half

* arrow

* i2c adjustments

* I2C slave and DC01 refractoring

- Cleaned up state machine of I2C slave driver
- Modified DC01 left to use already pressent I2C master driver
- Modified DC01 matrixes

* Fixed tabs to spaces

* Addition of Numpad

* Add keymaps

- Orthopad keymap for numpad module
- Numpad keymap for numpad module
- ISO, ANSI and HHKB version of keymap for right module

* Minor matrix.c fixes

* Update Readmes
This commit is contained in:
yiancar 2018-07-18 19:55:57 +03:00 • committed by Jack Humbert
parent 7e9a7af672
commit 72fd49b146
50 changed files with 3751 additions and 146 deletions
Download patch file Download diff file Expand all files Collapse all files

118
drivers/avr/i2c_master.c
View file

@ -15,15 +15,15 @@
void i2c_init(void)
{
TWSR = 0; /* no prescaler */
TWBR = (uint8_t)TWBR_val;
TWBR = (uint8_t)TWBR_val;
}
i2c_status_t i2c_start(uint8_t address, uint16_t timeout)
{
// reset TWI control register
TWCR = 0;
// transmit START condition
TWCR = (1<<TWINT) | (1<<TWSTA) | (1<<TWEN);
// reset TWI control register
TWCR = 0;
// transmit START condition
TWCR = (1<<TWINT) | (1<<TWSTA) | (1<<TWEN);
uint16_t timeout_timer = timer_read();
while( !(TWCR & (1<<TWINT)) ) {
@ -32,13 +32,13 @@ i2c_status_t i2c_start(uint8_t address, uint16_t timeout)
}
}
// check if the start condition was successfully transmitted
if(((TW_STATUS & 0xF8) != TW_START) && ((TW_STATUS & 0xF8) != TW_REP_START)){ return I2C_STATUS_ERROR; }
// check if the start condition was successfully transmitted
if(((TW_STATUS & 0xF8) != TW_START) && ((TW_STATUS & 0xF8) != TW_REP_START)){ return I2C_STATUS_ERROR; }
// load slave address into data register
TWDR = address;
// start transmission of address
TWCR = (1<<TWINT) | (1<<TWEN);
// load slave address into data register
TWDR = address;
// start transmission of address
TWCR = (1<<TWINT) | (1<<TWEN);
timeout_timer = timer_read();
while( !(TWCR & (1<<TWINT)) ) {
@ -47,19 +47,19 @@ i2c_status_t i2c_start(uint8_t address, uint16_t timeout)
}
}
// check if the device has acknowledged the READ / WRITE mode
uint8_t twst = TW_STATUS & 0xF8;
if ( (twst != TW_MT_SLA_ACK) && (twst != TW_MR_SLA_ACK) ) return I2C_STATUS_ERROR;
// check if the device has acknowledged the READ / WRITE mode
uint8_t twst = TW_STATUS & 0xF8;
if ( (twst != TW_MT_SLA_ACK) && (twst != TW_MR_SLA_ACK) ) return I2C_STATUS_ERROR;
return I2C_STATUS_SUCCESS;
return I2C_STATUS_SUCCESS;
}
i2c_status_t i2c_write(uint8_t data, uint16_t timeout)
{
// load data into data register
TWDR = data;
// start transmission of data
TWCR = (1<<TWINT) | (1<<TWEN);
// load data into data register
TWDR = data;
// start transmission of data
TWCR = (1<<TWINT) | (1<<TWEN);
uint16_t timeout_timer = timer_read();
while( !(TWCR & (1<<TWINT)) ) {
@ -68,16 +68,16 @@ i2c_status_t i2c_write(uint8_t data, uint16_t timeout)
}
}
if( (TW_STATUS & 0xF8) != TW_MT_DATA_ACK ){ return I2C_STATUS_ERROR; }
if( (TW_STATUS & 0xF8) != TW_MT_DATA_ACK ){ return I2C_STATUS_ERROR; }
return I2C_STATUS_SUCCESS;
return I2C_STATUS_SUCCESS;
}
int16_t i2c_read_ack(uint16_t timeout)
{
// start TWI module and acknowledge data after reception
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWEA);
// start TWI module and acknowledge data after reception
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWEA);
uint16_t timeout_timer = timer_read();
while( !(TWCR & (1<<TWINT)) ) {
@ -86,15 +86,15 @@ int16_t i2c_read_ack(uint16_t timeout)
}
}
// return received data from TWDR
return TWDR;
// return received data from TWDR
return TWDR;
}
int16_t i2c_read_nack(uint16_t timeout)
{
// start receiving without acknowledging reception
TWCR = (1<<TWINT) | (1<<TWEN);
// start receiving without acknowledging reception
TWCR = (1<<TWINT) | (1<<TWEN);
uint16_t timeout_timer = timer_read();
while( !(TWCR & (1<<TWINT)) ) {
@ -103,39 +103,39 @@ int16_t i2c_read_nack(uint16_t timeout)
}
}
// return received data from TWDR
return TWDR;
// return received data from TWDR
return TWDR;
}
i2c_status_t i2c_transmit(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout)
{
i2c_status_t status = i2c_start(address | I2C_WRITE, timeout);
if (status) return status;
for (uint16_t i = 0; i < length; i++) {
status = i2c_write(data[i], timeout);
if (status) return status;
}
status = i2c_stop(timeout);
if (status) return status;
return I2C_STATUS_SUCCESS;
for (uint16_t i = 0; i < length; i++) {
status = i2c_write(data[i], timeout);
if (status) return status;
}
status = i2c_stop(timeout);
if (status) return status;
return I2C_STATUS_SUCCESS;
}
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout)
{
i2c_status_t status = i2c_start(address | I2C_READ, timeout);
if (status) return status;
if (status) return status;
for (uint16_t i = 0; i < (length-1); i++) {
for (uint16_t i = 0; i < (length-1); i++) {
status = i2c_read_ack(timeout);
if (status >= 0) {
data[i] = status;
} else {
return status;
}
}
}
status = i2c_read_nack(timeout);
if (status >= 0 ) {
@ -147,47 +147,47 @@ i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16
status = i2c_stop(timeout);
if (status) return status;
return I2C_STATUS_SUCCESS;
return I2C_STATUS_SUCCESS;
}
i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout)
{
i2c_status_t status = i2c_start(devaddr | 0x00, timeout);
if (status) return status;
status = i2c_write(regaddr, timeout);
if (status) return status;
for (uint16_t i = 0; i < length; i++) {
status = i2c_write(regaddr, timeout);
if (status) return status;
for (uint16_t i = 0; i < length; i++) {
status = i2c_write(data[i], timeout);
if (status) return status;
}
if (status) return status;
}
status = i2c_stop(timeout);
status = i2c_stop(timeout);
if (status) return status;
return I2C_STATUS_SUCCESS;
return I2C_STATUS_SUCCESS;
}
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout)
{
i2c_status_t status = i2c_start(devaddr, timeout);
if (status) return status;
if (status) return status;
status = i2c_write(regaddr, timeout);
if (status) return status;
status = i2c_start(devaddr | 0x01, timeout);
if (status) return status;
if (status) return status;
for (uint16_t i = 0; i < (length-1); i++) {
status = i2c_read_ack(timeout);
for (uint16_t i = 0; i < (length-1); i++) {
status = i2c_read_ack(timeout);
if (status >= 0) {
data[i] = status;
} else {
return status;
}
}
}
status = i2c_read_nack(timeout);
if (status >= 0 ) {
@ -199,13 +199,13 @@ i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16
status = i2c_stop(timeout);
if (status) return status;
return I2C_STATUS_SUCCESS;
return I2C_STATUS_SUCCESS;
}
i2c_status_t i2c_stop(uint16_t timeout)
{
// transmit STOP condition
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO);
// transmit STOP condition
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO);
uint16_t timeout_timer = timer_read();
while(TWCR & (1<<TWSTO)) {
@ -215,4 +215,4 @@ i2c_status_t i2c_stop(uint16_t timeout)
}
return I2C_STATUS_SUCCESS;
}
}

2
drivers/avr/i2c_master.h
View file

@ -28,4 +28,4 @@ i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint1
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
i2c_status_t i2c_stop(uint16_t timeout);
#endif // I2C_MASTER_H
#endif // I2C_MASTER_H

134
drivers/avr/i2c_slave.c
View file

@ -5,96 +5,64 @@
#include <avr/io.h>
#include <util/twi.h>
#include <avr/interrupt.h>
#include <stdbool.h>
#include "i2c_slave.h"
void i2c_init(uint8_t address){
// load address into TWI address register
TWAR = (address << 1);
// set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt
TWCR = (1<<TWIE) | (1<<TWEA) | (1<<TWINT) | (1<<TWEN);
// load address into TWI address register
TWAR = (address << 1);
// set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt
TWCR = (1 << TWIE) | (1 << TWEA) | (1 << TWINT) | (1 << TWEN);
}
void i2c_stop(void){
// clear acknowledge and enable bits
TWCR &= ~( (1<<TWEA) | (1<<TWEN) );
// clear acknowledge and enable bits
TWCR &= ~((1 << TWEA) | (1 << TWEN));
}
ISR(TWI_vect){
// temporary stores the received data
uint8_t data;
// own address has been acknowledged
if( (TWSR & 0xF8) == TW_SR_SLA_ACK ){
buffer_address = 0xFF;
// clear TWI interrupt flag, prepare to receive next byte and acknowledge
TWCR |= (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
}
else if( (TWSR & 0xF8) == TW_SR_DATA_ACK ){ // data has been received in slave receiver mode
// save the received byte inside data
data = TWDR;
// check wether an address has already been transmitted or not
if(buffer_address == 0xFF){
buffer_address = data;
// clear TWI interrupt flag, prepare to receive next byte and acknowledge
TWCR |= (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
}
else{ // if a databyte has already been received
// store the data at the current address
rxbuffer[buffer_address] = data;
// increment the buffer address
buffer_address++;
// if there is still enough space inside the buffer
if(buffer_address < 0xFF){
// clear TWI interrupt flag, prepare to receive next byte and acknowledge
TWCR |= (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
}
else{
// Don't acknowledge
TWCR &= ~(1<<TWEA);
// clear TWI interrupt flag, prepare to receive last byte.
TWCR |= (1<<TWIE) | (1<<TWINT) | (1<<TWEN);
}
}
}
else if( (TWSR & 0xF8) == TW_ST_DATA_ACK ){ // device has been addressed to be a transmitter
// copy data from TWDR to the temporary memory
data = TWDR;
// if no buffer read address has been sent yet
if( buffer_address == 0xFF ){
buffer_address = data;
}
// copy the specified buffer address into the TWDR register for transmission
TWDR = txbuffer[buffer_address];
// increment buffer read address
buffer_address++;
// if there is another buffer address that can be sent
if(buffer_address < 0xFF){
// clear TWI interrupt flag, prepare to send next byte and receive acknowledge
TWCR |= (1<<TWIE) | (1<<TWINT) | (1<<TWEA) | (1<<TWEN);
}
else{
// Don't acknowledge
TWCR &= ~(1<<TWEA);
// clear TWI interrupt flag, prepare to receive last byte.
TWCR |= (1<<TWIE) | (1<<TWINT) | (1<<TWEN);
}
}
else{
// if none of the above apply prepare TWI to be addressed again
TWCR |= (1<<TWIE) | (1<<TWEA) | (1<<TWEN);
}
}
uint8_t ack = 1;
// temporary stores the received data
//uint8_t data;
switch(TW_STATUS){
case TW_SR_SLA_ACK:
// The device is now a slave receiver
slave_has_register_set = false;
break;
case TW_SR_DATA_ACK:
// This device is a slave receiver and has received data
// First byte is the location then the bytes will be writen in buffer with auto-incriment
if(!slave_has_register_set){
buffer_address = TWDR;
if (buffer_address >= RX_BUFFER_SIZE){ // address out of bounds dont ack
ack = 0;
buffer_address = 0;
}
slave_has_register_set = true; // address has been receaved now fill in buffer
} else {
rxbuffer[buffer_address] = TWDR;
buffer_address++;
}
break;
case TW_ST_SLA_ACK:
case TW_ST_DATA_ACK:
// This device is a slave transmitter and master has requested data
TWDR = txbuffer[buffer_address];
buffer_address++;
break;
case TW_BUS_ERROR:
// We got an error, reset i2c
TWCR = 0;
default:
break;
}
// Reset i2c state mahcine to be ready for next interrupt
TWCR |= (1 << TWIE) | (1 << TWINT) | (ack << TWEA) | (1 << TWEN);
}

10
drivers/avr/i2c_slave.h
View file

@ -8,12 +8,16 @@
#ifndef I2C_SLAVE_H
#define I2C_SLAVE_H
#define TX_BUFFER_SIZE 30
#define RX_BUFFER_SIZE 30
volatile uint8_t buffer_address;
volatile uint8_t txbuffer[0xFF];
volatile uint8_t rxbuffer[0xFF];
static volatile bool slave_has_register_set = false;
volatile uint8_t txbuffer[TX_BUFFER_SIZE];
volatile uint8_t rxbuffer[RX_BUFFER_SIZE];
void i2c_init(uint8_t address);
void i2c_stop(void);
ISR(TWI_vect);
#endif // I2C_SLAVE_H
#endif // I2C_SLAVE_H