Complete combining of PDI and TPI target communication code files, stub out TINY NVM controller functions.
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Dean Camera
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cfdab42dcf
commit
65fcebf478
10 changed files with 366 additions and 130 deletions
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@ -33,8 +33,8 @@
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* Target-related functions for the PDI Protocol decoder.
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*/
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#define INCLUDE_FROM_PDITARGET_C
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#include "PDITarget.h"
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#define INCLUDE_FROM_XPROGTARGET_C
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#include "XPROGTarget.h"
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#if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__)
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@ -49,7 +49,53 @@ volatile uint16_t SoftUSART_Data;
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#define SoftUSART_BitCount GPIOR2
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/** ISR to manage the software USART when bit-banged USART mode is selected. */
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/** ISR to manage the TPI software USART when bit-banged TPI USART mode is selected. */
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ISR(TIMER1_CAPT_vect, ISR_BLOCK)
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{
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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BITBANG_TPICLOCK_PIN |= BITBANG_TPICLOCK_MASK;
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/* If not sending or receiving, just exit */
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if (!(SoftUSART_BitCount))
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return;
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/* Check to see if we are at a rising or falling edge of the clock */
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if (BITBANG_TPICLOCK_PORT & BITBANG_TPICLOCK_MASK)
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{
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/* If at rising clock edge and we are in send mode, abort */
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if (IsSending)
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return;
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/* Wait for the start bit when receiving */
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if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK))
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return;
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access */
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if (BITBANG_TPIDATA_PIN & BITBANG_TPIDATA_MASK)
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SoftUSART_Data |= (1 << (BITS_IN_USART_FRAME - 1));
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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else
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{
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/* If at falling clock edge and we are in receive mode, abort */
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if (!IsSending)
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return;
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/* Set the data line to the next bit value */
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if (SoftUSART_Data & 0x01)
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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else
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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}
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}
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/** ISR to manage the PDI software USART when bit-banged PDI USART mode is selected. */
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ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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{
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/* Toggle CLOCK pin in a single cycle (see AVR datasheet) */
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@ -67,13 +113,13 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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return;
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/* Wait for the start bit when receiving */
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if ((SoftUSART_BitCount == BITS_IN_PDI_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
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if ((SoftUSART_BitCount == BITS_IN_USART_FRAME) && (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK))
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return;
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/* Shift in the bit one less than the frame size in position, so that the start bit will eventually
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* be discarded leaving the data to be byte-aligned for quick access */
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if (BITBANG_PDIDATA_PIN & BITBANG_PDIDATA_MASK)
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SoftUSART_Data |= (1 << (BITS_IN_PDI_FRAME - 1));
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SoftUSART_Data |= (1 << (BITS_IN_USART_FRAME - 1));
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SoftUSART_Data >>= 1;
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SoftUSART_BitCount--;
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@ -96,8 +142,50 @@ ISR(TIMER1_COMPA_vect, ISR_BLOCK)
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}
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#endif
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/** Enables the target's TPI interface, holding the target in reset until TPI mode is exited. */
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void XPROGTarget_EnableTargetTPI(void)
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{
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/* Set /RESET line low for at least 90ns to enable TPI functionality */
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RESET_LINE_DDR |= RESET_LINE_MASK;
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RESET_LINE_PORT &= ~RESET_LINE_MASK;
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asm volatile ("NOP"::);
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asm volatile ("NOP"::);
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set up the synchronous USART for XMEGA communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / 1000000UL);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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#else
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/* Set DATA and CLOCK lines to outputs */
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BITBANG_TPIDATA_DDR |= BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_DDR |= BITBANG_TPICLOCK_MASK;
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/* Set DATA line high for idle state */
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BITBANG_TPIDATA_PORT |= BITBANG_TPIDATA_MASK;
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/* Fire timer capture ISR every 100 cycles to manage the software USART */
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OCR1A = 80;
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TCCR1B = (1 << WGM13) | (1 << WGM12) | (1 << CS10);
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TIMSK1 = (1 << ICIE1);
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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#endif
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}
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/** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */
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void PDITarget_EnableTargetPDI(void)
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void XPROGTarget_EnableTargetPDI(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Set Tx and XCK as outputs, Rx as input */
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@ -116,8 +204,8 @@ void PDITarget_EnableTargetPDI(void)
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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/* Send two BREAKs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
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PDITarget_SendBreak();
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PDITarget_SendBreak();
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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#else
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/* Set DATA and CLOCK lines to outputs */
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BITBANG_PDIDATA_DDR |= BITBANG_PDIDATA_MASK;
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@ -134,13 +222,40 @@ void PDITarget_EnableTargetPDI(void)
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TIMSK1 = (1 << OCIE1A);
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/* Send two BREAKs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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PDITarget_SendBreak();
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PDITarget_SendBreak();
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XPROGTarget_SendBreak();
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XPROGTarget_SendBreak();
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#endif
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}
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/** Disables the target's TPI interface, exits programming mode and starts the target's application. */
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void XPROGTarget_DisableTargetTPI(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A |= (1 << TXC1) | (1 << RXC1);
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UCSR1B = 0;
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UCSR1C = 0;
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/* Set all USART lines as input, tristate */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
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/* Set DATA and CLOCK lines to inputs */
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BITBANG_TPIDATA_DDR &= ~BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_DDR &= ~BITBANG_TPICLOCK_MASK;
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/* Tristate DATA and CLOCK lines */
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BITBANG_TPIDATA_PORT &= ~BITBANG_TPIDATA_MASK;
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BITBANG_TPICLOCK_PORT &= ~BITBANG_TPICLOCK_MASK;
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#endif
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/* Tristate target /RESET line */
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RESET_LINE_DDR &= ~RESET_LINE_MASK;
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RESET_LINE_PORT &= ~RESET_LINE_MASK;
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}
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/** Disables the target's PDI interface, exits programming mode and starts the target's application. */
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void PDITarget_DisableTargetPDI(void)
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void XPROGTarget_DisableTargetPDI(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Turn off receiver and transmitter of the USART, clear settings */
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@ -166,7 +281,7 @@ void PDITarget_DisableTargetPDI(void)
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*
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* \param[in] Byte Byte to send through the USART
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*/
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void PDITarget_SendByte(const uint8_t Byte)
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void XPROGTarget_SendByte(const uint8_t Byte)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Switch to Tx mode if currently in Rx mode */
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@ -211,7 +326,7 @@ void PDITarget_SendByte(const uint8_t Byte)
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/* Data shifted out LSB first, START DATA PARITY STOP STOP */
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SoftUSART_Data = NewUSARTData;
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SoftUSART_BitCount = BITS_IN_PDI_FRAME;
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SoftUSART_BitCount = BITS_IN_USART_FRAME;
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#endif
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}
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@ -219,7 +334,7 @@ void PDITarget_SendByte(const uint8_t Byte)
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*
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* \return Received byte from the USART
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*/
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uint8_t PDITarget_ReceiveByte(void)
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uint8_t XPROGTarget_ReceiveByte(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Switch to Rx mode if currently in Tx mode */
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@ -253,7 +368,7 @@ uint8_t PDITarget_ReceiveByte(void)
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}
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/* Wait until a byte has been received before reading */
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SoftUSART_BitCount = BITS_IN_PDI_FRAME;
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SoftUSART_BitCount = BITS_IN_USART_FRAME;
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while (SoftUSART_BitCount);
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/* Throw away the parity and stop bits to leave only the data (start bit is already discarded) */
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@ -262,7 +377,7 @@ uint8_t PDITarget_ReceiveByte(void)
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}
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/** Sends a BREAK via the USART to the attached target, consisting of a full frame of idle bits. */
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void PDITarget_SendBreak(void)
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void XPROGTarget_SendBreak(void)
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{
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#if defined(XPROG_VIA_HARDWARE_USART)
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/* Switch to Tx mode if currently in Rx mode */
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@ -278,7 +393,7 @@ void PDITarget_SendBreak(void)
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}
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/* Need to do nothing for a full frame to send a BREAK */
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for (uint8_t i = 0; i < BITS_IN_PDI_FRAME; i++)
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for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
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{
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/* Wait for a full cycle of the clock */
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while (PIND & (1 << 5));
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@ -298,38 +413,8 @@ void PDITarget_SendBreak(void)
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/* Need to do nothing for a full frame to send a BREAK */
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SoftUSART_Data = 0x0FFF;
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SoftUSART_BitCount = BITS_IN_PDI_FRAME;
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SoftUSART_BitCount = BITS_IN_USART_FRAME;
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#endif
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}
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/** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC
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* calculation.
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*
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* \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
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*/
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bool PDITarget_WaitWhileNVMBusBusy(void)
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{
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TCNT0 = 0;
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TIFR0 = (1 << OCF1A);
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uint8_t TimeoutMS = PDI_NVM_TIMEOUT_MS;
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/* Poll the STATUS register to check to see if NVM access has been enabled */
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while (TimeoutMS)
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{
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/* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */
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PDITarget_SendByte(PDI_CMD_LDCS | PDI_STATUS_REG);
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if (PDITarget_ReceiveByte() & PDI_STATUS_NVM)
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return true;
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if (TIFR0 & (1 << OCF1A))
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{
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TIFR0 = (1 << OCF1A);
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TimeoutMS--;
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}
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}
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return false;
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}
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#endif
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