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Fix XPLAINBridge code broken during the changes to the Rescue Clock generation in the AVRISP-MKII clone project.

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Change over all low level host mode project's descriptor comparator routines to perform the descriptor casting in a temp variable to make the code clearer and easier to modify (despite being more verbose).
This commit is contained in:
Dean Camera 2010-11-02 11:16:36 +00:00
parent 3bf760ad7d
commit 5ce8380a7d
25 changed files with 380 additions and 287 deletions
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10
Projects/XPLAINBridge/Lib/SoftUART.c
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@ -67,7 +67,7 @@ void SoftUART_Init(void)
SoftUART_SetBaud(9600);
/* Setup reception timer compare ISR */
TIMSK2 = (1 << ICIE2);
TIMSK1 = (1 << ICIE1);
/* Setup transmission timer compare ISR and start the timer */
TIMSK3 = (1 << ICIE3);
@ -81,7 +81,7 @@ ISR(INT0_vect, ISR_BLOCK)
RX_BitsRemaining = 8;
/* Reset the bit reception timer */
TCNT2 = 0;
TCNT1 = 0;
/* Check to see that the pin is still low (prevents glitches from starting a frame reception) */
if (!(SRXPIN & (1 << SRX)))
@ -90,12 +90,12 @@ ISR(INT0_vect, ISR_BLOCK)
EIMSK = 0;
/* Start the reception timer */
TCCR2B = ((1 << CS20) | (1 << WGM23) | (1 << WGM22));
TCCR1B = ((1 << CS10) | (1 << WGM13) | (1 << WGM12));
}
}
/** ISR to manage the reception of bits to the software UART. */
ISR(TIMER2_CAPT_vect, ISR_BLOCK)
ISR(TIMER1_CAPT_vect, ISR_BLOCK)
{
/* Cache the current RX pin value for later checking */
uint8_t SRX_Cached = (SRXPIN & (1 << SRX));
@ -114,7 +114,7 @@ ISR(TIMER2_CAPT_vect, ISR_BLOCK)
else
{
/* Disable the reception timer as all data has now been received, re-enable start bit detection ISR */
TCCR2B = 0;
TCCR1B = 0;
EIFR = (1 << INTF0);
EIMSK = (1 << INT0);