Quantum Painter (#10174)
* Install dependencies before executing unit tests. * Split out UTF-8 decoder. * Fixup python formatting rules. * Add documentation for QGF/QFF and the RLE format used. * Add CLI commands for converting images and fonts. * Add stub rules.mk for QP. * Add stream type. * Add base driver and comms interfaces. * Add support for SPI, SPI+D/C comms drivers. * Include <qp.h> when enabled. * Add base support for SPI+D/C+RST panels, as well as concrete implementation of ST7789. * Add support for GC9A01. * Add support for ILI9341. * Add support for ILI9163. * Add support for SSD1351. * Implement qp_setpixel, including pixdata buffer management. * Implement qp_line. * Implement qp_rect. * Implement qp_circle. * Implement qp_ellipse. * Implement palette interpolation. * Allow for streams to work with either flash or RAM. * Image loading. * Font loading. * QGF palette loading. * Progressive decoder of pixel data supporting Raw+RLE, 1-,2-,4-,8-bpp monochrome and palette-based images. * Image drawing. * Animations. * Font rendering. * Check against 256 colours, dump out the loaded palette if debugging enabled. * Fix build. * AVR is not the intended audience. * `qmk format-c` * Generation fix. * First batch of docs. * More docs and examples. * Review comments. * Public API documentation.
This commit is contained in:
Nick Brassel
GitHub
parent
1dbbd2b6b0
commit
1f2b1dedcc
62 changed files with 7561 additions and 35 deletions
137
drivers/painter/comms/qp_comms_spi.c
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137
drivers/painter/comms/qp_comms_spi.c
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// Copyright 2021 Nick Brassel (@tzarc)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#ifdef QUANTUM_PAINTER_SPI_ENABLE
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# include "spi_master.h"
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# include "qp_comms_spi.h"
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Base SPI support
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bool qp_comms_spi_init(painter_device_t device) {
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struct painter_driver_t * driver = (struct painter_driver_t *)device;
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struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
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// Initialize the SPI peripheral
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spi_init();
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// Set up CS as output high
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setPinOutput(comms_config->chip_select_pin);
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writePinHigh(comms_config->chip_select_pin);
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return true;
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}
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bool qp_comms_spi_start(painter_device_t device) {
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struct painter_driver_t * driver = (struct painter_driver_t *)device;
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struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
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return spi_start(comms_config->chip_select_pin, comms_config->lsb_first, comms_config->mode, comms_config->divisor);
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}
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uint32_t qp_comms_spi_send_data(painter_device_t device, const void *data, uint32_t byte_count) {
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uint32_t bytes_remaining = byte_count;
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const uint8_t *p = (const uint8_t *)data;
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while (bytes_remaining > 0) {
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uint32_t bytes_this_loop = bytes_remaining < 1024 ? bytes_remaining : 1024;
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spi_transmit(p, bytes_this_loop);
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p += bytes_this_loop;
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bytes_remaining -= bytes_this_loop;
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}
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return byte_count - bytes_remaining;
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}
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void qp_comms_spi_stop(painter_device_t device) {
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struct painter_driver_t * driver = (struct painter_driver_t *)device;
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struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
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spi_stop();
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writePinHigh(comms_config->chip_select_pin);
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}
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const struct painter_comms_vtable_t spi_comms_vtable = {
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.comms_init = qp_comms_spi_init,
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.comms_start = qp_comms_spi_start,
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.comms_send = qp_comms_spi_send_data,
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.comms_stop = qp_comms_spi_stop,
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// SPI with D/C and RST pins
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# ifdef QUANTUM_PAINTER_SPI_DC_RESET_ENABLE
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bool qp_comms_spi_dc_reset_init(painter_device_t device) {
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if (!qp_comms_spi_init(device)) {
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return false;
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}
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struct painter_driver_t * driver = (struct painter_driver_t *)device;
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struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
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// Set up D/C as output low, if specified
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if (comms_config->dc_pin != NO_PIN) {
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setPinOutput(comms_config->dc_pin);
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writePinLow(comms_config->dc_pin);
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}
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// Set up RST as output, if specified, performing a reset in the process
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if (comms_config->reset_pin != NO_PIN) {
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setPinOutput(comms_config->reset_pin);
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writePinLow(comms_config->reset_pin);
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wait_ms(20);
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writePinHigh(comms_config->reset_pin);
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wait_ms(20);
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}
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return true;
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}
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uint32_t qp_comms_spi_dc_reset_send_data(painter_device_t device, const void *data, uint32_t byte_count) {
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struct painter_driver_t * driver = (struct painter_driver_t *)device;
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struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
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writePinHigh(comms_config->dc_pin);
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return qp_comms_spi_send_data(device, data, byte_count);
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}
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void qp_comms_spi_dc_reset_send_command(painter_device_t device, uint8_t cmd) {
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struct painter_driver_t * driver = (struct painter_driver_t *)device;
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struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
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writePinLow(comms_config->dc_pin);
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spi_write(cmd);
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}
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void qp_comms_spi_dc_reset_bulk_command_sequence(painter_device_t device, const uint8_t *sequence, size_t sequence_len) {
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for (size_t i = 0; i < sequence_len;) {
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uint8_t command = sequence[i];
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uint8_t delay = sequence[i + 1];
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uint8_t num_bytes = sequence[i + 2];
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qp_comms_spi_dc_reset_send_command(device, command);
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if (num_bytes > 0) {
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qp_comms_spi_dc_reset_send_data(device, &sequence[i + 3], num_bytes);
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}
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if (delay > 0) {
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wait_ms(delay);
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}
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i += (3 + num_bytes);
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}
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}
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const struct painter_comms_with_command_vtable_t spi_comms_with_dc_vtable = {
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.base =
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{
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.comms_init = qp_comms_spi_dc_reset_init,
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.comms_start = qp_comms_spi_start,
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.comms_send = qp_comms_spi_dc_reset_send_data,
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.comms_stop = qp_comms_spi_stop,
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},
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.send_command = qp_comms_spi_dc_reset_send_command,
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.bulk_command_sequence = qp_comms_spi_dc_reset_bulk_command_sequence,
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};
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# endif // QUANTUM_PAINTER_SPI_DC_RESET_ENABLE
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#endif // QUANTUM_PAINTER_SPI_ENABLE
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51
drivers/painter/comms/qp_comms_spi.h
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51
drivers/painter/comms/qp_comms_spi.h
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// Copyright 2021 Nick Brassel (@tzarc)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#ifdef QUANTUM_PAINTER_SPI_ENABLE
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# include <stdint.h>
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# include "gpio.h"
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# include "qp_internal.h"
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Base SPI support
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struct qp_comms_spi_config_t {
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pin_t chip_select_pin;
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uint16_t divisor;
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bool lsb_first;
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int8_t mode;
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};
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bool qp_comms_spi_init(painter_device_t device);
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bool qp_comms_spi_start(painter_device_t device);
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uint32_t qp_comms_spi_send_data(painter_device_t device, const void* data, uint32_t byte_count);
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void qp_comms_spi_stop(painter_device_t device);
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extern const struct painter_comms_vtable_t spi_comms_vtable;
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// SPI with D/C and RST pins
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# ifdef QUANTUM_PAINTER_SPI_DC_RESET_ENABLE
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struct qp_comms_spi_dc_reset_config_t {
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struct qp_comms_spi_config_t spi_config;
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pin_t dc_pin;
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pin_t reset_pin;
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};
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void qp_comms_spi_dc_reset_send_command(painter_device_t device, uint8_t cmd);
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uint32_t qp_comms_spi_dc_reset_send_data(painter_device_t device, const void* data, uint32_t byte_count);
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void qp_comms_spi_dc_reset_bulk_command_sequence(painter_device_t device, const uint8_t* sequence, size_t sequence_len);
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extern const struct painter_comms_with_command_vtable_t spi_comms_with_dc_vtable;
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# endif // QUANTUM_PAINTER_SPI_DC_RESET_ENABLE
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#endif // QUANTUM_PAINTER_SPI_ENABLE
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