Reverted Endpoint/Pipe non-sequential configuration hack, placed restriction on the configuration order instead to ensure maximum reliability.
Altered all low level device and host mode demos to ensure that endpoints and pipes are configured in ascending order properly. Rewrote all low level host mode demos' configuration descriptor parser code to ensure that pipes are enumerated in ascending order, and to ensure maximum compatibility with devices. Incremented all device mode demo's device descriptor revision numbers to ensure that any descriptor changes are re-fetched on machines which have enumerated previous versions.
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Dean Camera
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106 changed files with 838 additions and 796 deletions
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@ -43,8 +43,7 @@ bool Endpoint_ConfigureEndpoint_Prv(const uint8_t Number,
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const uint8_t UECFG0XData,
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const uint8_t UECFG1XData)
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{
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#if defined(CONTROL_ONLY_DEVICE)
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Endpoint_SelectEndpoint(ENDPOINT_CONTROLEP);
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Endpoint_SelectEndpoint(Number);
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Endpoint_EnableEndpoint();
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UECFG1X = 0;
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@ -52,51 +51,6 @@ bool Endpoint_ConfigureEndpoint_Prv(const uint8_t Number,
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UECFG1X = UECFG1XData;
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return Endpoint_IsConfigured();
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#else
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uint8_t UECFG0XTemp[ENDPOINT_TOTAL_ENDPOINTS];
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uint8_t UECFG1XTemp[ENDPOINT_TOTAL_ENDPOINTS];
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uint8_t UEIENXTemp[ENDPOINT_TOTAL_ENDPOINTS];
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for (uint8_t EPNum = 0; EPNum < ENDPOINT_TOTAL_ENDPOINTS; EPNum++)
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{
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Endpoint_SelectEndpoint(EPNum);
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UECFG0XTemp[EPNum] = UECFG0X;
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UECFG1XTemp[EPNum] = UECFG1X;
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UEIENXTemp[EPNum] = UEIENX;
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}
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UECFG0XTemp[Number] = UECFG0XData;
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UECFG1XTemp[Number] = UECFG1XData;
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UEIENXTemp[Number] = 0;
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for (uint8_t EPNum = 1; EPNum < ENDPOINT_TOTAL_ENDPOINTS; EPNum++)
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{
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Endpoint_SelectEndpoint(EPNum);
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UEIENX = 0;
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UEINTX = 0;
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UECFG1X = 0;
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Endpoint_DisableEndpoint();
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}
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for (uint8_t EPNum = 0; EPNum < ENDPOINT_TOTAL_ENDPOINTS; EPNum++)
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{
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if (!(UECFG1XTemp[EPNum] & (1 << ALLOC)))
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continue;
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Endpoint_SelectEndpoint(EPNum);
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Endpoint_EnableEndpoint();
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UECFG0X = UECFG0XTemp[EPNum];
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UECFG1X = UECFG1XTemp[EPNum];
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UEIENX = UEIENXTemp[EPNum];
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if (!(Endpoint_IsConfigured()))
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return false;
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}
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Endpoint_SelectEndpoint(Number);
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return true;
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#endif
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}
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void Endpoint_ClearEndpoints(void)
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@ -267,6 +267,9 @@
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* More banks uses more USB DPRAM, but offers better performance. Isochronous type
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* endpoints <b>must</b> have at least two banks.
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*
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* \note Endpoints <b>must</b> be configured in ascending order, or bank corruption will occur.
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* \n\n
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*
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* \note Certain models of USB AVR's endpoints may have different maximum packet sizes based on the endpoint's
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* index - refer to the chosen USB AVR's datasheet to determine the maximum bank size for each endpoint.
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* \n\n
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@ -442,7 +445,7 @@
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return ((UEINT & (1 << EndpointNumber)) ? true : false);
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}
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/** Determines if the selected IN endpoint is ready for a new packet.
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/** Determines if the selected IN endpoint is ready for a new packet to be sent to the host.
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*
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* \ingroup Group_EndpointPacketManagement
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*
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@ -454,7 +457,7 @@
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return ((UEINTX & (1 << TXINI)) ? true : false);
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}
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/** Determines if the selected OUT endpoint has received new packet.
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/** Determines if the selected OUT endpoint has received new packet from the host.
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*
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* \ingroup Group_EndpointPacketManagement
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*
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@ -44,61 +44,17 @@ bool Pipe_ConfigurePipe(const uint8_t Number,
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const uint16_t Size,
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const uint8_t Banks)
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{
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uint8_t UPCFG0XTemp[PIPE_TOTAL_PIPES];
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uint8_t UPCFG1XTemp[PIPE_TOTAL_PIPES];
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uint8_t UPCFG2XTemp[PIPE_TOTAL_PIPES];
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uint8_t UPCONXTemp[PIPE_TOTAL_PIPES];
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uint8_t UPINRQXTemp[PIPE_TOTAL_PIPES];
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uint8_t UPIENXTemp[PIPE_TOTAL_PIPES];
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for (uint8_t PNum = 0; PNum < PIPE_TOTAL_PIPES; PNum++)
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{
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Pipe_SelectPipe(PNum);
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UPCFG0XTemp[PNum] = UPCFG0X;
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UPCFG1XTemp[PNum] = UPCFG1X;
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UPCFG2XTemp[PNum] = UPCFG2X;
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UPCONXTemp[PNum] = UPCONX;
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UPINRQXTemp[PNum] = UPINRQX;
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UPIENXTemp[PNum] = UPIENX;
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}
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UPCFG0XTemp[Number] = ((Type << EPTYPE0) | Token | ((EndpointNumber & PIPE_EPNUM_MASK) << PEPNUM0));
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UPCFG1XTemp[Number] = ((1 << ALLOC) | Banks | Pipe_BytesToEPSizeMask(Size));
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UPCFG2XTemp[Number] = 0;
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UPCONXTemp[Number] = (1 << INMODE);
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UPINRQXTemp[Number] = 0;
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UPIENXTemp[Number] = 0;
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for (uint8_t PNum = 0; PNum < PIPE_TOTAL_PIPES; PNum++)
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{
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Pipe_SelectPipe(PNum);
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UPIENX = 0;
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UPINTX = 0;
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UPCFG1X = 0;
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Pipe_DisablePipe();
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}
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Pipe_SelectPipe(Number);
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Pipe_EnablePipe();
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for (uint8_t PNum = 0; PNum < PIPE_TOTAL_PIPES; PNum++)
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{
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if (!(UPCFG1XTemp[PNum] & (1 << ALLOC)))
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continue;
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Pipe_SelectPipe(PNum);
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Pipe_EnablePipe();
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UPCFG1X = 0;
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UPCFG0X = ((Type << EPTYPE0) | Token | ((EndpointNumber & PIPE_EPNUM_MASK) << PEPNUM0));
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UPCFG1X = ((1 << ALLOC) | Banks | Pipe_BytesToEPSizeMask(Size));
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UPCFG0X = UPCFG0XTemp[PNum];
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UPCFG1X = UPCFG1XTemp[PNum];
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UPCFG2X = UPCFG2XTemp[PNum];
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UPCONX |= UPCONXTemp[PNum];
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UPINRQX = UPINRQXTemp[PNum];
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UPIENX = UPIENXTemp[PNum];
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Pipe_SetInfiniteINRequests();
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if (!(Pipe_IsConfigured()))
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return false;
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}
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Pipe_SelectPipe(Number);
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return true;
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return Pipe_IsConfigured();
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}
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void Pipe_ClearPipes(void)
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@ -462,7 +462,7 @@
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return ((UPINTX & (1 << RWAL)) ? true : false);
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}
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/** Determines if an IN request has been received on the currently selected pipe.
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/** Determines if a packet has been received on the currently selected IN pipe from the attached device.
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*
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* \ingroup Group_PipePacketManagement
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*
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@ -474,7 +474,7 @@
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return ((UPINTX & (1 << RXINI)) ? true : false);
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}
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/** Determines if the currently selected pipe is ready to send an OUT request.
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/** Determines if the currently selected OUT pipe is ready to send an OUT packet to the attached device.
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*
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* \ingroup Group_PipePacketManagement
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*
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@ -839,6 +839,9 @@
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* uses more USB DPRAM, but offers better performance. Isochronous type pipes <b>must</b>
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* have at least two banks.
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*
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* \note Endpoints <b>must</b> be configured in ascending order, or bank corruption will occur.
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* \n\n
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*
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* \note Certain models of USB AVR's pipes may have different maximum packet sizes based on the pipe's
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* index - refer to the chosen USB AVR's datasheet to determine the maximum bank size for each pipe.
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* \n\n
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