haptic: further naming cleanups (#21682)
This commit is contained in:
Ryan
GitHub
parent
c9fa2006d9
commit
0b802defd4
21 changed files with 424 additions and 469 deletions
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@ -41,58 +41,58 @@ void drv2605l_init(void) {
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// drv2605l_write(DRV2605L_REG_FEEDBACK_CTRL,0xB6);
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#if FB_ERM_LRA == 0
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#if DRV2605L_FB_ERM_LRA == 0
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/* ERM settings */
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drv2605l_write(DRV2605L_REG_RATED_VOLTAGE, (RATED_VOLTAGE / 21.33) * 1000);
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# if ERM_OPEN_LOOP == 0
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drv2605l_write(DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE, (((V_PEAK * (DRIVE_TIME + BLANKING_TIME + IDISS_TIME)) / 0.02133) / (DRIVE_TIME - 0.0003)));
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# elif ERM_OPEN_LOOP == 1
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drv2605l_write(DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE, (V_PEAK / 0.02196));
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drv2605l_write(DRV2605L_REG_RATED_VOLTAGE, (DRV2605L_RATED_VOLTAGE / 21.33) * 1000);
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# if DRV2605L_ERM_OPEN_LOOP == 0
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drv2605l_write(DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE, (((DRV2605L_V_PEAK * (DRV2605L_DRIVE_TIME + DRV2605L_BLANKING_TIME + DRV2605L_IDISS_TIME)) / 0.02133) / (DRV2605L_DRIVE_TIME - 0.0003)));
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# elif DRV2605L_ERM_OPEN_LOOP == 1
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drv2605l_write(DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE, (DRV2605L_V_PEAK / 0.02196));
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# endif
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#elif FB_ERM_LRA == 1
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drv2605l_write(DRV2605L_REG_RATED_VOLTAGE, ((V_RMS * sqrt(1 - ((4 * ((150 + (SAMPLE_TIME * 50)) * 0.000001)) + 0.0003) * F_LRA) / 0.02071)));
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# if LRA_OPEN_LOOP == 0
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drv2605l_write(DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE, ((V_PEAK / sqrt(1 - (F_LRA * 0.0008)) / 0.02133)));
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# elif LRA_OPEN_LOOP == 1
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drv2605l_write(DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE, (V_PEAK / 0.02196));
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#elif DRV2605L_FB_ERM_LRA == 1
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drv2605l_write(DRV2605L_REG_RATED_VOLTAGE, ((DRV2605L_V_RMS * sqrt(1 - ((4 * ((150 + (DRV2605L_SAMPLE_TIME * 50)) * 0.000001)) + 0.0003) * DRV2605L_F_LRA) / 0.02071)));
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# if DRV2605L_LRA_OPEN_LOOP == 0
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drv2605l_write(DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE, ((DRV2605L_V_PEAK / sqrt(1 - (DRV2605L_F_LRA * 0.0008)) / 0.02133)));
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# elif DRV2605L_LRA_OPEN_LOOP == 1
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drv2605l_write(DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE, (DRV2605L_V_PEAK / 0.02196));
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# endif
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#endif
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DRVREG_FBR FB_SET;
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FB_SET.Bits.ERM_LRA = FB_ERM_LRA;
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FB_SET.Bits.BRAKE_FACTOR = FB_BRAKEFACTOR;
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FB_SET.Bits.LOOP_GAIN = FB_LOOPGAIN;
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FB_SET.Bits.BEMF_GAIN = 0; /* auto-calibration populates this field*/
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drv2605l_write(DRV2605L_REG_FEEDBACK_CTRL, (uint8_t)FB_SET.Byte);
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drv2605l_reg_feedback_ctrl_t reg_feedback_ctrl;
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reg_feedback_ctrl.bits.ERM_LRA = DRV2605L_FB_ERM_LRA;
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reg_feedback_ctrl.bits.BRAKE_FACTOR = DRV2605L_FB_BRAKEFACTOR;
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reg_feedback_ctrl.bits.LOOP_GAIN = DRV2605L_FB_LOOPGAIN;
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reg_feedback_ctrl.bits.BEMF_GAIN = 0; /* auto-calibration populates this field*/
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drv2605l_write(DRV2605L_REG_FEEDBACK_CTRL, (uint8_t)reg_feedback_ctrl.raw);
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DRVREG_CTRL1 C1_SET;
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C1_SET.Bits.C1_DRIVE_TIME = DRIVE_TIME;
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C1_SET.Bits.C1_AC_COUPLE = AC_COUPLE;
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C1_SET.Bits.C1_STARTUP_BOOST = STARTUP_BOOST;
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drv2605l_write(DRV2605L_REG_CTRL1, (uint8_t)C1_SET.Byte);
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drv2605l_reg_ctrl1_t reg_ctrl1;
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reg_ctrl1.bits.C1_DRIVE_TIME = DRV2605L_DRIVE_TIME;
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reg_ctrl1.bits.C1_AC_COUPLE = DRV2605L_AC_COUPLE;
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reg_ctrl1.bits.C1_STARTUP_BOOST = DRV2605L_STARTUP_BOOST;
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drv2605l_write(DRV2605L_REG_CTRL1, (uint8_t)reg_ctrl1.raw);
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DRVREG_CTRL2 C2_SET;
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C2_SET.Bits.C2_BIDIR_INPUT = BIDIR_INPUT;
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C2_SET.Bits.C2_BRAKE_STAB = BRAKE_STAB;
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C2_SET.Bits.C2_SAMPLE_TIME = SAMPLE_TIME;
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C2_SET.Bits.C2_BLANKING_TIME = BLANKING_TIME;
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C2_SET.Bits.C2_IDISS_TIME = IDISS_TIME;
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drv2605l_write(DRV2605L_REG_CTRL2, (uint8_t)C2_SET.Byte);
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drv2605l_reg_ctrl2_t reg_ctrl2;
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reg_ctrl2.bits.C2_BIDIR_INPUT = DRV2605L_BIDIR_INPUT;
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reg_ctrl2.bits.C2_BRAKE_STAB = DRV2605L_BRAKE_STAB;
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reg_ctrl2.bits.C2_SAMPLE_TIME = DRV2605L_SAMPLE_TIME;
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reg_ctrl2.bits.C2_BLANKING_TIME = DRV2605L_BLANKING_TIME;
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reg_ctrl2.bits.C2_IDISS_TIME = DRV2605L_IDISS_TIME;
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drv2605l_write(DRV2605L_REG_CTRL2, (uint8_t)reg_ctrl2.raw);
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DRVREG_CTRL3 C3_SET;
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C3_SET.Bits.C3_LRA_OPEN_LOOP = LRA_OPEN_LOOP;
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C3_SET.Bits.C3_N_PWM_ANALOG = N_PWM_ANALOG;
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C3_SET.Bits.C3_LRA_DRIVE_MODE = LRA_DRIVE_MODE;
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C3_SET.Bits.C3_DATA_FORMAT_RTO = DATA_FORMAT_RTO;
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C3_SET.Bits.C3_SUPPLY_COMP_DIS = SUPPLY_COMP_DIS;
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C3_SET.Bits.C3_ERM_OPEN_LOOP = ERM_OPEN_LOOP;
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C3_SET.Bits.C3_NG_THRESH = NG_THRESH;
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drv2605l_write(DRV2605L_REG_CTRL3, (uint8_t)C3_SET.Byte);
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drv2605l_reg_ctrl3_t reg_ctrl3;
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reg_ctrl3.bits.C3_LRA_OPEN_LOOP = DRV2605L_LRA_OPEN_LOOP;
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reg_ctrl3.bits.C3_N_PWM_ANALOG = DRV2605L_N_PWM_ANALOG;
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reg_ctrl3.bits.C3_LRA_DRIVE_MODE = DRV2605L_LRA_DRIVE_MODE;
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reg_ctrl3.bits.C3_DATA_FORMAT_RTO = DRV2605L_DATA_FORMAT_RTO;
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reg_ctrl3.bits.C3_SUPPLY_COMP_DIS = DRV2605L_SUPPLY_COMP_DIS;
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reg_ctrl3.bits.C3_ERM_OPEN_LOOP = DRV2605L_ERM_OPEN_LOOP;
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reg_ctrl3.bits.C3_NG_THRESH = DRV2605L_NG_THRESH;
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drv2605l_write(DRV2605L_REG_CTRL3, (uint8_t)reg_ctrl3.raw);
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DRVREG_CTRL4 C4_SET;
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C4_SET.Bits.C4_ZC_DET_TIME = ZC_DET_TIME;
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C4_SET.Bits.C4_AUTO_CAL_TIME = AUTO_CAL_TIME;
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drv2605l_write(DRV2605L_REG_CTRL4, (uint8_t)C4_SET.Byte);
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drv2605l_reg_ctrl4_t reg_ctrl4;
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reg_ctrl4.bits.C4_ZC_DET_TIME = DRV2605L_ZC_DET_TIME;
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reg_ctrl4.bits.C4_AUTO_CAL_TIME = DRV2605L_AUTO_CAL_TIME;
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drv2605l_write(DRV2605L_REG_CTRL4, (uint8_t)reg_ctrl4.raw);
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drv2605l_write(DRV2605L_REG_LIBRARY_SELECTION, DRV2605L_LIBRARY);
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@ -22,42 +22,42 @@
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/* Initialization settings
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* Feedback Control Settings */
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#ifndef FB_ERM_LRA
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# define FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/
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#ifndef DRV2605L_FB_ERM_LRA
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# define DRV2605L_FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/
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#endif
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#ifndef FB_BRAKEFACTOR
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# define FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */
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#ifndef DRV2605L_FB_BRAKEFACTOR
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# define DRV2605L_FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */
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#endif
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#ifndef FB_LOOPGAIN
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# define FB_LOOPGAIN 1 /* For Low:0, Medium:1, High:2, Very High:3 */
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#ifndef DRV2605L_FB_LOOPGAIN
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# define DRV2605L_FB_LOOPGAIN 1 /* For Low:0, Medium:1, High:2, Very High:3 */
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#endif
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/* LRA specific settings */
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#if FB_ERM_LRA == 1
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# ifndef V_RMS
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# define V_RMS 2.0
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#if DRV2605L_FB_ERM_LRA == 1
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# ifndef DRV2605L_V_RMS
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# define DRV2605L_V_RMS 2.0
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# endif
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# ifndef V_PEAK
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# define V_PEAK 2.1
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# ifndef DRV2605L_V_PEAK
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# define DRV2605L_V_PEAK 2.1
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# endif
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# ifndef F_LRA
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# define F_LRA 205
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# ifndef DRV2605L_F_LRA
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# define DRV2605L_F_LRA 205
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# endif
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# ifndef RATED_VOLTAGE
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# define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
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# ifndef DRV2605L_RATED_VOLTAGE
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# define DRV2605L_RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
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# endif
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#endif
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#ifndef RATED_VOLTAGE
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# define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
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#ifndef DRV2605L_RATED_VOLTAGE
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# define DRV2605L_RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
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#endif
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#ifndef V_PEAK
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# define V_PEAK 2.8
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#ifndef DRV2605L_V_PEAK
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# define DRV2605L_V_PEAK 2.8
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#endif
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/* Library Selection */
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#ifndef DRV2605L_LIBRARY
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# if FB_ERM_LRA == 1
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# if DRV2605L_FB_ERM_LRA == 1
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# define DRV2605L_LIBRARY 6 /* For Empty:0' TS2200 library A to D:1-5, LRA Library: 6 */
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# else
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# define DRV2605L_LIBRARY 1
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@ -65,69 +65,69 @@
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#endif
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#ifndef DRV2605L_GREETING
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# define DRV2605L_GREETING alert_750ms
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# define DRV2605L_GREETING DRV2605L_EFFECT_750_MS_ALERT_100
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#endif
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#ifndef DRV2605L_DEFAULT_MODE
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# define DRV2605L_DEFAULT_MODE strong_click1
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# define DRV2605L_DEFAULT_MODE DRV2605L_EFFECT_STRONG_CLICK_1_100
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#endif
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/* Control 1 register settings */
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#ifndef DRIVE_TIME
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# define DRIVE_TIME 25
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#ifndef DRV2605L_DRIVE_TIME
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# define DRV2605L_DRIVE_TIME 25
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#endif
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#ifndef AC_COUPLE
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# define AC_COUPLE 0
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#ifndef DRV2605L_AC_COUPLE
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# define DRV2605L_AC_COUPLE 0
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#endif
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#ifndef STARTUP_BOOST
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# define STARTUP_BOOST 1
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#ifndef DRV2605L_STARTUP_BOOST
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# define DRV2605L_STARTUP_BOOST 1
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#endif
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/* Control 2 Settings */
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#ifndef BIDIR_INPUT
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# define BIDIR_INPUT 1
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#ifndef DRV2605L_BIDIR_INPUT
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# define DRV2605L_BIDIR_INPUT 1
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#endif
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#ifndef BRAKE_STAB
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# define BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */
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#ifndef DRV2605L_BRAKE_STAB
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# define DRV2605L_BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */
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#endif
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#ifndef SAMPLE_TIME
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# define SAMPLE_TIME 3
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#ifndef DRV2605L_SAMPLE_TIME
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# define DRV2605L_SAMPLE_TIME 3
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#endif
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#ifndef BLANKING_TIME
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# define BLANKING_TIME 1
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#ifndef DRV2605L_BLANKING_TIME
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# define DRV2605L_BLANKING_TIME 1
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#endif
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#ifndef IDISS_TIME
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# define IDISS_TIME 1
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#ifndef DRV2605L_IDISS_TIME
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# define DRV2605L_IDISS_TIME 1
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#endif
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/* Control 3 settings */
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#ifndef NG_THRESH
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# define NG_THRESH 2
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#ifndef DRV2605L_NG_THRESH
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# define DRV2605L_NG_THRESH 2
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#endif
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#ifndef ERM_OPEN_LOOP
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# define ERM_OPEN_LOOP 1
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#ifndef DRV2605L_ERM_OPEN_LOOP
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# define DRV2605L_ERM_OPEN_LOOP 1
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#endif
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#ifndef SUPPLY_COMP_DIS
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# define SUPPLY_COMP_DIS 0
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#ifndef DRV2605L_SUPPLY_COMP_DIS
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# define DRV2605L_SUPPLY_COMP_DIS 0
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#endif
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#ifndef DATA_FORMAT_RTO
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# define DATA_FORMAT_RTO 0
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#ifndef DRV2605L_DATA_FORMAT_RTO
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# define DRV2605L_DATA_FORMAT_RTO 0
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#endif
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#ifndef LRA_DRIVE_MODE
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# define LRA_DRIVE_MODE 0
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#ifndef DRV2605L_LRA_DRIVE_MODE
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# define DRV2605L_LRA_DRIVE_MODE 0
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#endif
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#ifndef N_PWM_ANALOG
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# define N_PWM_ANALOG 0
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#ifndef DRV2605L_N_PWM_ANALOG
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# define DRV2605L_N_PWM_ANALOG 0
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#endif
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#ifndef LRA_OPEN_LOOP
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# define LRA_OPEN_LOOP 0
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#ifndef DRV2605L_LRA_OPEN_LOOP
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# define DRV2605L_LRA_OPEN_LOOP 0
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#endif
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/* Control 4 settings */
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#ifndef ZC_DET_TIME
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# define ZC_DET_TIME 0
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#ifndef DRV2605L_ZC_DET_TIME
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# define DRV2605L_ZC_DET_TIME 0
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#endif
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#ifndef AUTO_CAL_TIME
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# define AUTO_CAL_TIME 3
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#ifndef DRV2605L_AUTO_CAL_TIME
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# define DRV2605L_AUTO_CAL_TIME 3
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#endif
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#define DRV2605L_I2C_ADDRESS 0x5A
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@ -175,203 +175,169 @@ void drv2605l_rtp_init(void);
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void drv2605l_amplitude(const uint8_t amplitude);
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void drv2605l_pulse(const uint8_t sequence);
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typedef enum DRV_EFFECT {
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clear_sequence,
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strong_click,
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strong_click_60,
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strong_click_30,
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sharp_click,
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sharp_click_60,
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sharp_click_30,
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soft_bump,
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soft_bump_60,
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soft_bump_30,
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dbl_click,
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dbl_click_60,
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trp_click,
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soft_fuzz,
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strong_buzz,
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alert_750ms,
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alert_1000ms,
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strong_click1,
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strong_click2_80,
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strong_click3_60,
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strong_click4_30,
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medium_click1,
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medium_click2_80,
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medium_click3_60,
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sharp_tick1,
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sharp_tick2_80,
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sharp_tick3_60,
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sh_dblclick_str,
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sh_dblclick_str_80,
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sh_dblclick_str_60,
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sh_dblclick_str_30,
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sh_dblclick_med,
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sh_dblclick_med_80,
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sh_dblclick_med_60,
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sh_dblsharp_tick,
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sh_dblsharp_tick_80,
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sh_dblsharp_tick_60,
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lg_dblclick_str,
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lg_dblclick_str_80,
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lg_dblclick_str_60,
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lg_dblclick_str_30,
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lg_dblclick_med,
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lg_dblclick_med_80,
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lg_dblclick_med_60,
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lg_dblsharp_tick,
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lg_dblsharp_tick_80,
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lg_dblsharp_tick_60,
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buzz,
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buzz_80,
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buzz_60,
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buzz_40,
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buzz_20,
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pulsing_strong,
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pulsing_strong_80,
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pulsing_medium,
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pulsing_medium_80,
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pulsing_sharp,
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pulsing_sharp_80,
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transition_click,
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transition_click_80,
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transition_click_60,
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transition_click_40,
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transition_click_20,
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transition_click_10,
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transition_hum,
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transition_hum_80,
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transition_hum_60,
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transition_hum_40,
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transition_hum_20,
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transition_hum_10,
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transition_rampdown_long_smooth1,
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transition_rampdown_long_smooth2,
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transition_rampdown_med_smooth1,
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transition_rampdown_med_smooth2,
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transition_rampdown_short_smooth1,
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transition_rampdown_short_smooth2,
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transition_rampdown_long_sharp1,
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transition_rampdown_long_sharp2,
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transition_rampdown_med_sharp1,
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transition_rampdown_med_sharp2,
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transition_rampdown_short_sharp1,
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transition_rampdown_short_sharp2,
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transition_rampup_long_smooth1,
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transition_rampup_long_smooth2,
|
||||
transition_rampup_med_smooth1,
|
||||
transition_rampup_med_smooth2,
|
||||
transition_rampup_short_smooth1,
|
||||
transition_rampup_short_smooth2,
|
||||
transition_rampup_long_sharp1,
|
||||
transition_rampup_long_sharp2,
|
||||
transition_rampup_med_sharp1,
|
||||
transition_rampup_med_sharp2,
|
||||
transition_rampup_short_sharp1,
|
||||
transition_rampup_short_sharp2,
|
||||
transition_rampdown_long_smooth1_50,
|
||||
transition_rampdown_long_smooth2_50,
|
||||
transition_rampdown_med_smooth1_50,
|
||||
transition_rampdown_med_smooth2_50,
|
||||
transition_rampdown_short_smooth1_50,
|
||||
transition_rampdown_short_smooth2_50,
|
||||
transition_rampdown_long_sharp1_50,
|
||||
transition_rampdown_long_sharp2_50,
|
||||
transition_rampdown_med_sharp1_50,
|
||||
transition_rampdown_med_sharp2_50,
|
||||
transition_rampdown_short_sharp1_50,
|
||||
transition_rampdown_short_sharp2_50,
|
||||
transition_rampup_long_smooth1_50,
|
||||
transition_rampup_long_smooth2_50,
|
||||
transition_rampup_med_smooth1_50,
|
||||
transition_rampup_med_smooth2_50,
|
||||
transition_rampup_short_smooth1_50,
|
||||
transition_rampup_short_smooth2_50,
|
||||
transition_rampup_long_sharp1_50,
|
||||
transition_rampup_long_sharp2_50,
|
||||
transition_rampup_med_sharp1_50,
|
||||
transition_rampup_med_sharp2_50,
|
||||
transition_rampup_short_sharp1_50,
|
||||
transition_rampup_short_sharp2_50,
|
||||
long_buzz_for_programmatic_stopping,
|
||||
smooth_hum1_50,
|
||||
smooth_hum2_40,
|
||||
smooth_hum3_30,
|
||||
smooth_hum4_20,
|
||||
smooth_hum5_10,
|
||||
drv_effect_max
|
||||
} DRV_EFFECT;
|
||||
typedef enum drv2605l_effect_t {
|
||||
DRV2605L_EFFECT_CLEAR_SEQUENCE,
|
||||
DRV2605L_EFFECT_STRONG_CLICK_100,
|
||||
DRV2605L_EFFECT_STRONG_CLICK_60,
|
||||
DRV2605L_EFFECT_STRONG_CLICK_30,
|
||||
DRV2605L_EFFECT_SHARP_CLICK_100,
|
||||
DRV2605L_EFFECT_SHARP_CLICK_60,
|
||||
DRV2605L_EFFECT_SHARP_CLICK_30,
|
||||
DRV2605L_EFFECT_SOFT_BUMP_100,
|
||||
DRV2605L_EFFECT_SOFT_BUMP_60,
|
||||
DRV2605L_EFFECT_SOFT_BUMP_30,
|
||||
DRV2605L_EFFECT_DOUBLE_CLICK_100,
|
||||
DRV2605L_EFFECT_DOUBLE_CLICK_60,
|
||||
DRV2605L_EFFECT_TRIPLE_CLICK_100,
|
||||
DRV2605L_EFFECT_SOFT_FUZZ_60,
|
||||
DRV2605L_EFFECT_STRONG_BUZZ_100,
|
||||
DRV2605L_EFFECT_750_MS_ALERT_100,
|
||||
DRV2605L_EFFECT_1000_MS_ALERT_100,
|
||||
DRV2605L_EFFECT_STRONG_CLICK_1_100,
|
||||
DRV2605L_EFFECT_STRONG_CLICK_2_80,
|
||||
DRV2605L_EFFECT_STRONG_CLICK_3_60,
|
||||
DRV2605L_EFFECT_STRONG_CLICK_4_30,
|
||||
DRV2605L_EFFECT_MEDIUM_CLICK_1_100,
|
||||
DRV2605L_EFFECT_MEDIUM_CLICK_2_80,
|
||||
DRV2605L_EFFECT_MEDIUM_CLICK_3_60,
|
||||
DRV2605L_EFFECT_SHARP_TICK_1_100,
|
||||
DRV2605L_EFFECT_SHARP_TICK_2_80,
|
||||
DRV2605L_EFFECT_SHARP_TICK_3_60,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_STRONG_1_100,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_STRONG_2_80,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_STRONG_3_60,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_STRONG_4_30,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_MEDIUM_1_100,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_MEDIUM_2_80,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_CLICK_MEDIUM_3_60,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_SHARP_TICK_1_100,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_SHARP_TICK_2_80,
|
||||
DRV2605L_EFFECT_SHORT_DOUBLE_SHARP_TICK_3_60,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_STRONG_1_100,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_STRONG_2_80,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_STRONG_3_60,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_STRONG_4_30,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_MEDIUM_1_100,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_MEDIUM_2_80,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_CLICK_MEDIUM_3_60,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_TICK_1_100,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_TICK_2_80,
|
||||
DRV2605L_EFFECT_LONG_DOUBLE_SHARP_TICK_3_60,
|
||||
DRV2605L_EFFECT_BUZZ_1_100,
|
||||
DRV2605L_EFFECT_BUZZ_2_80,
|
||||
DRV2605L_EFFECT_BUZZ_3_60,
|
||||
DRV2605L_EFFECT_BUZZ_4_40,
|
||||
DRV2605L_EFFECT_BUZZ_5_20,
|
||||
DRV2605L_EFFECT_PULSING_STRONG_1_100,
|
||||
DRV2605L_EFFECT_PULSING_STRONG_2_60,
|
||||
DRV2605L_EFFECT_PULSING_MEDIUM_1_100,
|
||||
DRV2605L_EFFECT_PULSING_MEDIUM_2_60,
|
||||
DRV2605L_EFFECT_PULSING_SHARP_1_100,
|
||||
DRV2605L_EFFECT_PULSING_SHARP_2_60,
|
||||
DRV2605L_EFFECT_TRANSITION_CLICK_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_CLICK_2_80,
|
||||
DRV2605L_EFFECT_TRANSITION_CLICK_3_60,
|
||||
DRV2605L_EFFECT_TRANSITION_CLICK_4_40,
|
||||
DRV2605L_EFFECT_TRANSITION_CLICK_5_20,
|
||||
DRV2605L_EFFECT_TRANSITION_CLICK_6_10,
|
||||
DRV2605L_EFFECT_TRANSITION_HUM_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_HUM_2_80,
|
||||
DRV2605L_EFFECT_TRANSITION_HUM_3_60,
|
||||
DRV2605L_EFFECT_TRANSITION_HUM_4_40,
|
||||
DRV2605L_EFFECT_TRANSITION_HUM_5_20,
|
||||
DRV2605L_EFFECT_TRANSITION_HUM_6_10,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SMOOTH_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SMOOTH_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SMOOTH_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SMOOTH_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SHARP_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SHARP_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SHARP_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SHARP_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SHARP_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SHARP_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SMOOTH_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SMOOTH_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SMOOTH_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SMOOTH_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SMOOTH_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SMOOTH_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SHARP_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SHARP_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SHARP_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SHARP_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SHARP_1_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SHARP_2_100,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SMOOTH_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SMOOTH_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SMOOTH_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SMOOTH_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SHARP_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_LONG_SHARP_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SHARP_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_MEDIUM_SHARP_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SHARP_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_DOWN_SHORT_SHARP_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SMOOTH_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SMOOTH_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SMOOTH_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SMOOTH_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SMOOTH_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SMOOTH_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SHARP_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_LONG_SHARP_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SHARP_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_MEDIUM_SHARP_2_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SHARP_1_50,
|
||||
DRV2605L_EFFECT_TRANSITION_RAMP_UP_SHORT_SHARP_2_50,
|
||||
DRV2605L_EFFECT_LONG_BUZZ_FOR_PROGRAMMATIC_STOPPING,
|
||||
DRV2605L_EFFECT_SMOOTH_HUM_1_50,
|
||||
DRV2605L_EFFECT_SMOOTH_HUM_2_40,
|
||||
DRV2605L_EFFECT_SMOOTH_HUM_3_30,
|
||||
DRV2605L_EFFECT_SMOOTH_HUM_4_20,
|
||||
DRV2605L_EFFECT_SMOOTH_HUM_5_10,
|
||||
DRV2605L_EFFECT_COUNT
|
||||
} drv2605l_effect_t;
|
||||
|
||||
/* Register bit array unions */
|
||||
|
||||
typedef union DRVREG_STATUS { /* register 0x00 */
|
||||
uint8_t Byte;
|
||||
struct {
|
||||
uint8_t OC_DETECT : 1; /* set to 1 when overcurrent event is detected */
|
||||
uint8_t OVER_TEMP : 1; /* set to 1 when device exceeds temp threshold */
|
||||
uint8_t FB_STS : 1; /* set to 1 when feedback controller has timed out */
|
||||
/* auto-calibration routine and diagnostic result
|
||||
* result | auto-calibation | diagnostic |
|
||||
* 0 | passed | actuator func normal |
|
||||
* 1 | failed | actuator func fault* |
|
||||
* * actuator is not present or is shorted, timing out, or giving out–of-range back-EMF */
|
||||
uint8_t DIAG_RESULT : 1;
|
||||
uint8_t : 1;
|
||||
uint8_t DEVICE_ID : 3; /* Device IDs 3: DRV2605 4: DRV2604 5: DRV2604L 6: DRV2605L */
|
||||
} Bits;
|
||||
} DRVREG_STATUS;
|
||||
|
||||
typedef union DRVREG_MODE { /* register 0x01 */
|
||||
uint8_t Byte;
|
||||
struct {
|
||||
uint8_t MODE : 3; /* Mode setting */
|
||||
uint8_t : 3;
|
||||
uint8_t STANDBY : 1; /* 0:standby 1:ready */
|
||||
} Bits;
|
||||
} DRVREG_MODE;
|
||||
|
||||
typedef union DRVREG_WAIT {
|
||||
uint8_t Byte;
|
||||
struct {
|
||||
uint8_t WAIT_MODE : 1; /* Set to 1 to interpret as wait for next 7 bits x10ms */
|
||||
uint8_t WAIT_TIME : 7;
|
||||
} Bits;
|
||||
} DRVREG_WAIT;
|
||||
|
||||
typedef union DRVREG_FBR { /* register 0x1A */
|
||||
uint8_t Byte;
|
||||
typedef union { /* register 0x1A */
|
||||
uint8_t raw;
|
||||
struct {
|
||||
uint8_t BEMF_GAIN : 2;
|
||||
uint8_t LOOP_GAIN : 2;
|
||||
uint8_t BRAKE_FACTOR : 3;
|
||||
uint8_t ERM_LRA : 1;
|
||||
} Bits;
|
||||
} DRVREG_FBR;
|
||||
} bits;
|
||||
} drv2605l_reg_feedback_ctrl_t;
|
||||
|
||||
typedef union DRVREG_CTRL1 { /* register 0x1B */
|
||||
uint8_t Byte;
|
||||
typedef union { /* register 0x1B */
|
||||
uint8_t raw;
|
||||
struct {
|
||||
uint8_t C1_DRIVE_TIME : 5;
|
||||
uint8_t C1_AC_COUPLE : 1;
|
||||
uint8_t : 1;
|
||||
uint8_t C1_STARTUP_BOOST : 1;
|
||||
} Bits;
|
||||
} DRVREG_CTRL1;
|
||||
} bits;
|
||||
} drv2605l_reg_ctrl1_t;
|
||||
|
||||
typedef union DRVREG_CTRL2 { /* register 0x1C */
|
||||
uint8_t Byte;
|
||||
typedef union { /* register 0x1C */
|
||||
uint8_t raw;
|
||||
struct {
|
||||
uint8_t C2_IDISS_TIME : 2;
|
||||
uint8_t C2_BLANKING_TIME : 2;
|
||||
uint8_t C2_SAMPLE_TIME : 2;
|
||||
uint8_t C2_BRAKE_STAB : 1;
|
||||
uint8_t C2_BIDIR_INPUT : 1;
|
||||
} Bits;
|
||||
} DRVREG_CTRL2;
|
||||
} bits;
|
||||
} drv2605l_reg_ctrl2_t;
|
||||
|
||||
typedef union DRVREG_CTRL3 { /* register 0x1D */
|
||||
uint8_t Byte;
|
||||
typedef union { /* register 0x1D */
|
||||
uint8_t raw;
|
||||
struct {
|
||||
uint8_t C3_LRA_OPEN_LOOP : 1;
|
||||
uint8_t C3_N_PWM_ANALOG : 1;
|
||||
|
|
@ -380,11 +346,11 @@ typedef union DRVREG_CTRL3 { /* register 0x1D */
|
|||
uint8_t C3_SUPPLY_COMP_DIS : 1;
|
||||
uint8_t C3_ERM_OPEN_LOOP : 1;
|
||||
uint8_t C3_NG_THRESH : 2;
|
||||
} Bits;
|
||||
} DRVREG_CTRL3;
|
||||
} bits;
|
||||
} drv2605l_reg_ctrl3_t;
|
||||
|
||||
typedef union DRVREG_CTRL4 { /* register 0x1E */
|
||||
uint8_t Byte;
|
||||
typedef union { /* register 0x1E */
|
||||
uint8_t raw;
|
||||
struct {
|
||||
uint8_t C4_OTP_PROGRAM : 1;
|
||||
uint8_t : 1;
|
||||
|
|
@ -392,16 +358,5 @@ typedef union DRVREG_CTRL4 { /* register 0x1E */
|
|||
uint8_t : 1;
|
||||
uint8_t C4_AUTO_CAL_TIME : 2;
|
||||
uint8_t C4_ZC_DET_TIME : 2;
|
||||
} Bits;
|
||||
} DRVREG_CTRL4;
|
||||
|
||||
typedef union DRVREG_CTRL5 { /* register 0x1F */
|
||||
uint8_t Byte;
|
||||
struct {
|
||||
uint8_t C5_IDISS_TIME : 2;
|
||||
uint8_t C5_BLANKING_TIME : 2;
|
||||
uint8_t C5_PLAYBACK_INTERVAL : 1;
|
||||
uint8_t C5_LRA_AUTO_OPEN_LOOP : 1;
|
||||
uint8_t C5_AUTO_OL_CNT : 2;
|
||||
} Bits;
|
||||
} DRVREG_CTRL5;
|
||||
} bits;
|
||||
} drv2605l_reg_ctrl4_t;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue