Oops - revert commit of an incomplete port of the AVRISP-MKII project.
This commit is contained in:
Dean Camera
parent
ea922c98d1
commit
0b6d5467bc
19 changed files with 156 additions and 324 deletions
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@ -46,22 +46,18 @@ void XPROGTarget_EnableTargetPDI(void)
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{
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IsSending = false;
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#if (ARCH == ARCH_AVR8)
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set DATA line high for at least 90ns to disable /RESET functionality */
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PORTD |= (1 << 3);
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Delay_MS(1);
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/* Set DATA line high for at least 90ns to disable /RESET functionality */
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PORTD |= (1 << 3);
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_delay_us(1);
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/* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
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UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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#endif
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/* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
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UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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/* Send two IDLEs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
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XPROGTarget_SendIdle();
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@ -73,23 +69,19 @@ void XPROGTarget_EnableTargetTPI(void)
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{
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IsSending = false;
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#if (ARCH == ARCH_AVR8)
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/* Set /RESET line low for at least 400ns to enable TPI functionality */
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AUX_LINE_DDR |= AUX_LINE_MASK;
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AUX_LINE_PORT &= ~AUX_LINE_MASK;
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Delay_MS(1);
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/* Set /RESET line low for at least 400ns to enable TPI functionality */
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AUX_LINE_DDR |= AUX_LINE_MASK;
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AUX_LINE_PORT &= ~AUX_LINE_MASK;
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_delay_us(1);
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set Tx and XCK as outputs, Rx as input */
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DDRD |= (1 << 5) | (1 << 3);
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DDRD &= ~(1 << 2);
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/* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */
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UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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#endif
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/* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */
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UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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/* Send two IDLEs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
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XPROGTarget_SendIdle();
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@ -102,18 +94,14 @@ void XPROGTarget_DisableTargetPDI(void)
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/* Switch to Rx mode to ensure that all pending transmissions are complete */
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XPROGTarget_SetRxMode();
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#if (ARCH == ARCH_AVR8)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A = ((1 << TXC1) | (1 << RXC1));
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UCSR1B = 0;
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UCSR1C = 0;
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A = ((1 << TXC1) | (1 << RXC1));
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UCSR1B = 0;
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UCSR1C = 0;
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/* Tristate all pins */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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#endif
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/* Tristate all pins */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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}
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/** Disables the target's TPI interface, exits programming mode and starts the target's application. */
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@ -122,22 +110,18 @@ void XPROGTarget_DisableTargetTPI(void)
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/* Switch to Rx mode to ensure that all pending transmissions are complete */
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XPROGTarget_SetRxMode();
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#if (ARCH == ARCH_AVR8)
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A |= (1 << TXC1) | (1 << RXC1);
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UCSR1B = 0;
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UCSR1C = 0;
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/* Turn off receiver and transmitter of the USART, clear settings */
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UCSR1A |= (1 << TXC1) | (1 << RXC1);
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UCSR1B = 0;
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UCSR1C = 0;
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/* Set all USART lines as inputs, tristate */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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/* Tristate target /RESET line */
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AUX_LINE_DDR &= ~AUX_LINE_MASK;
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AUX_LINE_PORT &= ~AUX_LINE_MASK;
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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#endif
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/* Set all USART lines as inputs, tristate */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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/* Tristate target /RESET line */
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AUX_LINE_DDR &= ~AUX_LINE_MASK;
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AUX_LINE_PORT &= ~AUX_LINE_MASK;
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}
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/** Sends a byte via the USART.
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@ -150,14 +134,10 @@ void XPROGTarget_SendByte(const uint8_t Byte)
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if (!(IsSending))
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XPROGTarget_SetTxMode();
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#if (ARCH == ARCH_AVR8)
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/* Wait until there is space in the hardware Tx buffer before writing */
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while (!(UCSR1A & (1 << UDRE1)));
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UCSR1A |= (1 << TXC1);
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UDR1 = Byte;
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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#endif
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/* Wait until there is space in the hardware Tx buffer before writing */
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while (!(UCSR1A & (1 << UDRE1)));
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UCSR1A |= (1 << TXC1);
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UDR1 = Byte;
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}
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/** Receives a byte via the software USART, blocking until data is received.
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@ -170,15 +150,10 @@ uint8_t XPROGTarget_ReceiveByte(void)
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if (IsSending)
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XPROGTarget_SetRxMode();
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#if (ARCH == ARCH_AVR8)
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/* Wait until a byte has been received before reading */
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while (!(UCSR1A & (1 << RXC1)) && !(TimeoutExpired));
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/* Wait until a byte has been received before reading */
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while (!(UCSR1A & (1 << RXC1)) && !(TimeoutExpired));
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return UDR1;
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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return 0;
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#endif
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return UDR1;
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}
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/** Sends an IDLE via the USART to the attached target, consisting of a full frame of idle bits. */
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@ -188,52 +163,40 @@ void XPROGTarget_SendIdle(void)
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if (!(IsSending))
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XPROGTarget_SetTxMode();
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#if (ARCH == ARCH_AVR8)
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/* Need to do nothing for a full frame to send an IDLE */
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for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
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{
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/* Wait for a full cycle of the clock */
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while (PIND & (1 << 5));
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while (!(PIND & (1 << 5)));
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}
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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#endif
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/* Need to do nothing for a full frame to send an IDLE */
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for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
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{
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/* Wait for a full cycle of the clock */
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while (PIND & (1 << 5));
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while (!(PIND & (1 << 5)));
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}
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}
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static void XPROGTarget_SetTxMode(void)
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{
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#if (ARCH == ARCH_AVR8)
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/* Wait for a full cycle of the clock */
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while (PIND & (1 << 5));
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while (!(PIND & (1 << 5)));
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/* Wait for a full cycle of the clock */
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while (PIND & (1 << 5));
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while (!(PIND & (1 << 5)));
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PORTD |= (1 << 3);
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DDRD |= (1 << 3);
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PORTD |= (1 << 3);
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DDRD |= (1 << 3);
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UCSR1B &= ~(1 << RXEN1);
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UCSR1B |= (1 << TXEN1);
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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#endif
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UCSR1B &= ~(1 << RXEN1);
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UCSR1B |= (1 << TXEN1);
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IsSending = true;
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}
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static void XPROGTarget_SetRxMode(void)
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{
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#if (ARCH == ARCH_AVR8)
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while (!(UCSR1A & (1 << TXC1)));
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UCSR1A |= (1 << TXC1);
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while (!(UCSR1A & (1 << TXC1)));
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UCSR1A |= (1 << TXC1);
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UCSR1B &= ~(1 << TXEN1);
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UCSR1B |= (1 << RXEN1);
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UCSR1B &= ~(1 << TXEN1);
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UCSR1B |= (1 << RXEN1);
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DDRD &= ~(1 << 3);
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PORTD &= ~(1 << 3);
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#elif (ARCH == ARCH_UC3)
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// TODO: FIXME
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#endif
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DDRD &= ~(1 << 3);
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PORTD &= ~(1 << 3);
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IsSending = false;
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}
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