Add svn:eol-style property to source files, so that the line endings are correctly converted to the target system's native end of line style.
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Dean Camera
parent
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839 changed files with 274562 additions and 274562 deletions
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@ -1,143 +1,143 @@
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/*
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LUFA Library
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Copyright (C) Dean Camera, 2010.
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dean [at] fourwalledcubicle [dot] com
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www.fourwalledcubicle.com
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*/
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/*
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Copyright 2010 David Prentice (david.prentice [at] farming [dot] uk)
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Copyright 2010 Peter Danneger
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Copyright 2010 Dean Camera (dean [at] fourwalledcubicle [dot] com)
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Permission to use, copy, modify, distribute, and sell this
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software and its documentation for any purpose is hereby granted
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without fee, provided that the above copyright notice appear in
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all copies and that both that the copyright notice and this
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permission notice and warranty disclaimer appear in supporting
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documentation, and that the name of the author not be used in
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advertising or publicity pertaining to distribution of the
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software without specific, written prior permission.
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The author disclaim all warranties with regard to this
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software, including all implied warranties of merchantability
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and fitness. In no event shall the author be liable for any
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special, indirect or consequential damages or any damages
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whatsoever resulting from loss of use, data or profits, whether
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in an action of contract, negligence or other tortious action,
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arising out of or in connection with the use or performance of
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this software.
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*/
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#include "SoftUART.h"
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volatile uint8_t srx_done, stx_count;
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volatile uint8_t srx_data, srx_mask, srx_tmp, stx_data;
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uint8_t SoftUART_IsReady(void)
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{
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return !(stx_count);
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}
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uint8_t SoftUART_TxByte(uint8_t Byte)
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{
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while (stx_count);
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stx_data = ~Byte;
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stx_count = 10;
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return Byte;
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}
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uint8_t SoftUART_IsReceived(void)
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{
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return srx_done;
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}
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uint8_t SoftUART_RxByte(void)
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{
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while (!(srx_done));
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srx_done = 0;
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return srx_data;
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}
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void SoftUART_Init(void)
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{
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OCR2B = TCNT2 + 1; // force first compare
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TCCR2A = (1 << COM2B1) | (1 << COM2B0); // T1 mode 0
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TCCR2B = (1 << FOC2B) | (1 << CS21); // CLK/8, T1 mode 0
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TIMSK2 = (1 << OCIE2B); // enable tx and wait for start
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EICRA = (1 << ISC01); // -ve edge
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EIMSK = (1 << INT0); // enable INT0 interrupt
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stx_count = 0; // nothing to send
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srx_done = 0; // nothing received
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STXPORT |= 1 << STX; // TX output
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STXDDR |= 1 << STX; // TX output
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SRXPORT |= (1 << SRX); // pullup on INT0
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}
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/* ISR to detect the start of a bit being sent from the transmitter. */
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ISR(INT0_vect)
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{
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OCR2A = TCNT2 + (BIT_TIME / 8 * 3 / 2); // scan 1.5 bits after start
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srx_tmp = 0; // clear bit storage
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srx_mask = 1; // bit mask
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TIFR2 = (1 << OCF2A); // clear pending interrupt
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if (!(SRXPIN & (1 << SRX))) // still low
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{
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TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit
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EIMSK &= ~(1 << INT0);
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}
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}
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/* ISR to manage the reception of bits to the transmitter. */
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ISR(TIMER2_COMPA_vect)
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{
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if (srx_mask)
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{
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if (SRXPIN & (1 << SRX))
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srx_tmp |= srx_mask;
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srx_mask <<= 1;
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OCR2A += BIT_TIME / 8; // next bit slice
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}
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else
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{
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srx_done = 1; // mark rx data valid
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srx_data = srx_tmp; // store rx data
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TIMSK2 = (1 << OCIE2B); // enable tx and wait for start
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EIMSK |= (1 << INT0); // enable START irq
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EIFR = (1 << INTF0); // clear any pending
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}
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}
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/* ISR to manage the transmission of bits to the receiver. */
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ISR(TIMER2_COMPB_vect)
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{
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OCR2B += BIT_TIME / 8; // next bit slice
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if (stx_count)
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{
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if (--stx_count != 9) // no start bit
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{
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if (!(stx_data & 1)) // test inverted data
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TCCR2A = (1 << COM2B1) | (1 << COM2B0);
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else
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TCCR2A = (1 << COM2B1);
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stx_data >>= 1; // shift zero in from left
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}
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else
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{
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TCCR2A = (1 << COM2B1); // START bit
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}
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}
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}
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/*
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LUFA Library
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Copyright (C) Dean Camera, 2010.
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dean [at] fourwalledcubicle [dot] com
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www.fourwalledcubicle.com
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*/
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/*
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Copyright 2010 David Prentice (david.prentice [at] farming [dot] uk)
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Copyright 2010 Peter Danneger
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Copyright 2010 Dean Camera (dean [at] fourwalledcubicle [dot] com)
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Permission to use, copy, modify, distribute, and sell this
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software and its documentation for any purpose is hereby granted
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without fee, provided that the above copyright notice appear in
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all copies and that both that the copyright notice and this
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permission notice and warranty disclaimer appear in supporting
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documentation, and that the name of the author not be used in
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advertising or publicity pertaining to distribution of the
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software without specific, written prior permission.
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The author disclaim all warranties with regard to this
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software, including all implied warranties of merchantability
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and fitness. In no event shall the author be liable for any
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special, indirect or consequential damages or any damages
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whatsoever resulting from loss of use, data or profits, whether
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in an action of contract, negligence or other tortious action,
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arising out of or in connection with the use or performance of
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this software.
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*/
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#include "SoftUART.h"
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volatile uint8_t srx_done, stx_count;
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volatile uint8_t srx_data, srx_mask, srx_tmp, stx_data;
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uint8_t SoftUART_IsReady(void)
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{
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return !(stx_count);
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}
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uint8_t SoftUART_TxByte(uint8_t Byte)
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{
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while (stx_count);
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stx_data = ~Byte;
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stx_count = 10;
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return Byte;
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}
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uint8_t SoftUART_IsReceived(void)
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{
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return srx_done;
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}
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uint8_t SoftUART_RxByte(void)
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{
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while (!(srx_done));
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srx_done = 0;
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return srx_data;
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}
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void SoftUART_Init(void)
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{
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OCR2B = TCNT2 + 1; // force first compare
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TCCR2A = (1 << COM2B1) | (1 << COM2B0); // T1 mode 0
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TCCR2B = (1 << FOC2B) | (1 << CS21); // CLK/8, T1 mode 0
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TIMSK2 = (1 << OCIE2B); // enable tx and wait for start
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EICRA = (1 << ISC01); // -ve edge
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EIMSK = (1 << INT0); // enable INT0 interrupt
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stx_count = 0; // nothing to send
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srx_done = 0; // nothing received
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STXPORT |= 1 << STX; // TX output
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STXDDR |= 1 << STX; // TX output
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SRXPORT |= (1 << SRX); // pullup on INT0
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}
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/* ISR to detect the start of a bit being sent from the transmitter. */
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ISR(INT0_vect)
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{
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OCR2A = TCNT2 + (BIT_TIME / 8 * 3 / 2); // scan 1.5 bits after start
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srx_tmp = 0; // clear bit storage
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srx_mask = 1; // bit mask
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TIFR2 = (1 << OCF2A); // clear pending interrupt
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if (!(SRXPIN & (1 << SRX))) // still low
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{
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TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit
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EIMSK &= ~(1 << INT0);
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}
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}
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/* ISR to manage the reception of bits to the transmitter. */
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ISR(TIMER2_COMPA_vect)
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{
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if (srx_mask)
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{
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if (SRXPIN & (1 << SRX))
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srx_tmp |= srx_mask;
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srx_mask <<= 1;
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OCR2A += BIT_TIME / 8; // next bit slice
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}
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else
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{
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srx_done = 1; // mark rx data valid
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srx_data = srx_tmp; // store rx data
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TIMSK2 = (1 << OCIE2B); // enable tx and wait for start
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EIMSK |= (1 << INT0); // enable START irq
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EIFR = (1 << INTF0); // clear any pending
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}
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}
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/* ISR to manage the transmission of bits to the receiver. */
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ISR(TIMER2_COMPB_vect)
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{
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OCR2B += BIT_TIME / 8; // next bit slice
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if (stx_count)
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{
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if (--stx_count != 9) // no start bit
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{
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if (!(stx_data & 1)) // test inverted data
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TCCR2A = (1 << COM2B1) | (1 << COM2B0);
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else
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TCCR2A = (1 << COM2B1);
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stx_data >>= 1; // shift zero in from left
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}
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else
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{
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TCCR2A = (1 << COM2B1); // START bit
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}
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}
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}
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